User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 757
UG585 (v1.11) September 27, 2016
Chapter 30: XADC Interface
3. Wait until the Command FIFO becomes empty. Wait until devcfg.XADCIF_MSTS [CFIFOE] = 1.
Note: For every write to the devcfg.XADCIF_CMDFIFO register, data is shifted into the
devcfg.XADCIF_RDFIFO register (Read Data FIFO).
Example: Read the V
CCPAUX
value from the XADC
This example reads the current V
CCPAUX
value from the XADC V
CCPAUX
status register.
1. Prepare command. Prepare the command as described in section 30.4.3 Command Preparation
for reading the XADC V
CCPAUX
Status register (0x0E).
2. Write data to Command FIFO. Write data formatted in step 1 to the devcfg.XADCIF_CMDFIFO
register.
3. Wait until the Command FIFO becomes empty. Wait until devcfg.XADCIF_MSTS [CFIFOE] = 1.
4. Read dummy data from the Read Data FIFO. Read the devcfg.XADCIF_RDFIFO register.
5. Format data. Prepare Command for No operation as described in 30.4.3 Command Preparation.
6. Write data to the Command FIFO. Write the formatted data in step 5 to the
devcfg.XADCIF_CMDFIFO register.
7. Read the Read Data FIFO. Read the devcfg.XADCIF_RDFIFO register.
Note: After a read command has been sent to the XADC, the corresponding read data will be
available during the next shift period. Therefore, one dummy command write (as shown in step 5) is
always needed to push out the last read data.
30.4.2 Interrupts
Example: Configure and Manage Alarm 5 (V
CCPAUX
)
This example configures the XADC registers to set alarm thresholds, operating mode, and enables
the Alarm 5 (VCCPAUX) interrupt in the PS-XADC interface. The XADC hard macro has to be operated
in Independent mode because alarms are not enabled in Default mode (refer to the XADC Operating
Modes section of UG480
, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1
MSPS Analog-to-Digital Converter User Guide.
1. Prepare commands. Prepare commands as described in section 30.4.3 Command Preparation
for writing to the XADC hard macro alarm threshold registers (V
CCPAUX
Upper-0x5A and V
CCPAUX
Lower-0x5E) with the required thresholds and XADC Config_Reg1 (0x41) to set the XADC in
Independent mode.
2. Write commands to the Command FIFO. Write the commands prepared in step 1 to the
devcfg.XADCIF_CMDFIFO register.
3. Enable the Alarm 5 interrupt in the PS-XADC interface. Write devcfg.XADCIF_INT_MASK
[M_ALM] =7Eh.
4. Check if Alarm 5 is triggered. Poll for devcfg.XADCIF_INT_STS [M_ALM] = 1.
5. Clear the Alarm 5 interrupt. Write devcfg.XADCIF_INT_STS [M_ALM] = 1.
6. Disable the Alarm 0 interrupt. Write devcfg.XADCIF_INT_MASK [M_ALM] = 7Fh