User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 773
UG585 (v1.11) September 27, 2016
Chapter 32: Device Secure Boot
Once the SPK has been authenticated, the BootROM calculates the SHA-256 hash value for the FSBL
stored in OCM. The FSBL is authenticated using the SPK. If the authentication passes, a secure FSBL
is then decrypted using the AES or a non-secure FSBL will start execution.
32.2.6 Boot Image and Bitstream Encryption
Boot images are assembled and encrypted using software provided by Xilinx, bootgen. A FSBL and
any additional PS images or PL bitstreams along with the encryption key and authentication
signature must be supplied to bootgen. The correct headers are generated automatically when
bootgen builds the boot image.
32.2.7 Boot Image and Bitstream Decryption and Authentication
For PS image and PL bitstream decryption, Xilinx uses the advanced encryption standard (AES) in
cipher block chaining (CBC) mode with a 256-bit key. PS images and PL bitstreams are authenticated
with a keyed-hashed message authentication code (HMAC) using the SHA-256 hash algorithm. When
the BootROM detects that the FSBL image is encrypted, it enables the decryption and authentication
engines within the PL. Both are enabled or disabled in tandem and cannot be separated.
Subsequent PS images do not have to be encrypted. Once an encrypted FSBL has been loaded, it is
“trusted” and can then load a non-encrypted second stage boot loader or application directly to
OCM. Loading of non-encrypted PS images after a secure boot is not recommended and should only
be done after fully evaluating the system-level security.
32.2.8 HMAC Signature
HMAC authentication is performed whenever the AES is used. When creating an encrypted boot
image, the HMAC key must be provided to the bootgen software. The HMAC key and signature are
then encrypted with the boot file. Unlike the AES key, the HMAC key and signature are part of the
encrypted image. During the on-chip decryption process, the HMAC signature is extracted from the
image and used by the authentication algorithm. No on-chip storage for the HMAC key is required.
32.2.9 AES Key Management
The AES encryption key is stored on-chip within the PL. It can be loaded into either volatile
battery-backed RAM (BBRAM) or in non-volatile eFuse storage. The keys are loaded into the PL via
the JTAG interface. (See UG470
, 7 Series FPGAs Configuration User Guide for more information.)