User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 778
UG585 (v1.11) September 27, 2016
Appendix A: Additional Resources
A.2 Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all
stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips.
A.3 References
A.3.1 Zynq-7000 AP SoC Documents
Refer to the following Zynq-7000 AP SoC documents for further reference:
°
DS190, Zynq-7000 AP SoC Product Overview
°
DS187, Zynq-7000 AP SoC (7z007s, 7z012s, 7z014s, 7z010, 7z015, and 7z020): AC and DC
Switching Characteristics Data Sheet
°
DS191, Zynq-7000 AP SoC (7z030, 7z045, and 7z100): AC and DC Switching Characteristics
Data Sheet
°
UG865, Zynq-7000 AP SoC Packaging and Pinout Specifications
°
UG821, Zynq-7000 AP SoC Software Developers Guide
°
UG933, Zynq-7000 AP SoC PCB Design and Pin Planning Guide
These user guides and additional relevant information can be found on the Xilinx Zynq-7000 AP SoC
product page:
http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/soc/zy
nq-7000.html
A.3.2 PL Documents – Device and Boards
To learn more about the PL resources, refer to the following 7 Series FPGA User Guides:
°
DS821, Xilinx LogiCORE IP 7 Series FPGAs Integrated Block for PCI Express Product
Specification
°
UG471, Xilinx 7 Series FPGAs SelectIO Resources User Guide
°
UG472, Xilinx 7 Series FPGAs Clocking Resources User Guide
°
UG473, Xilinx 7 Series FPGAs Memory Resources User Guide
°
UG474, Xilinx 7 Series FPGAs Configurable Logic Block User Guide
°
UG476, Xilinx 7 Series FPGAs GTX Transceiver User Guide
°
UG477, Xilinx 7 Series FPGAs Integrated Block v1.3 for PCI Express User Guide
°
UG479, Xilinx 7 Series FPGAs DSP48E1 User Guide
°
UG480, Xilinx 7 Series FPGAs XADC User Guide
°
UG483, Xilinx 7-Series FPGAs PCB and Pin Planning Guide