User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 780
UG585 (v1.11) September 27, 2016
Appendix A: Additional Resources
Xilinx Embedded Development Kit (EDK)
http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools/embedd
ed_development_kit__edk.html
ChipScope Pro Documentation
http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools/chipscop
e_pro.html
A.3.7 Xilinx Problem Solvers
http://www.xilinx.com/support/troubleshoot.htm
A.3.8 Third-Party IP and Standards Documents
To learn about functional details related to vendor IP cores contained in Zynq-7000 devices or
related international interface standards, refer the following documents:
Note: ARM documents can be found at: http://infocenter.arm.com/help/index.jsp
°
ARM AMBA Level 2 Cache Controller (L2C-310) TRM (also called PL310)
°
ARM AMBA Specification Revision 2.0, 1999 (IHI 0011A)
°
ARM Architecture Reference Manual (Need to register with ARM)
°
ARM Cortex-A Series Programmer's Guide
°
ARM Cortex-A9 Technical Reference Manual, Revision r3p0
°
ARM Cortex-A9 MPCore Technical Reference Manual, Revision r3p0 (DDI0407F) – includes
descriptions for accelerator coherency port (ACP), CPU private timers and watchdog timers
(AWDT), event bus, general interrupt controller (GIC), and snoop control unit (SCU)
°
ARM Cortex-A9 NEON Media Processing Engine Technical Reference Manual, Revision r3p0
°
ARM Cortex-A9 Floating-Point Unit Technical Reference Manual, Revision r3p0
°
ARM CoreSight v1.0 Architecture Specification – includes descriptions for ATB Bus, and
Authentication
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ARM CoreSight Program Flow Trace Architecture Specification
°
ARM Debug Interface v5.1 Architecture Specification
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ARM Debug Interface v5.1 Architecture Specification Supplement
°
ARM CoreSight Components TRM – includes descriptions for embedded cross trigger (ECT),
embedded trace buffer (ETB), instrumentation trace macrocell (ITM), debug access port
(DAP), and trace port interface unit (TPIU)
°
ARM CoreSight PTM-A9 TRM
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ARM CoreSight Trace Memory Controller Technical Reference Manual
°
ARM Generic Interrupt Controller v1.0 Architecture Specification (IHI 0048B)
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ARM Generic Interrupt Controller PL390 Technical Reference Manual (DDI0416B)