User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 785
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
50 modules, 2036 registers.
gem1 GEM 0xE000C000 Gigabit Ethernet Controller
gpio gpio
0xE000A000 General Purpose Input / Output
gpv_qos301_c
pu
qos301
0xF8946000 AMBA Network Interconnect Advanced Quality of
Service (QoS-301), CPU-to-DDR
gpv_qos301_d
mac
qos301
0xF8947000 AMBA Network Interconnect Advanced Quality of
Service (QoS-301), DMAC
gpv_qos301_io
u
qos301
0xF8948000 AMBA Network Interconnect Advanced Quality of
Service (QoS-301), IOU
gpv_trustzone nic301_addr_r
egion_ctrl_regi
sters
0xF8900000 AMBA NIC301 TrustZone.
i2c0 IIC
0xE0004000 Inter Integrated Circuit (I2C)
i2c1 IIC
0xE0005000 Inter Integrated Circuit (I2C)
l2cache L2Cpl310
0xF8F02000 L2 cache PL310
mpcore mpcore
0xF8F00000 Mpcore - SCU, Interrupt controller, Counters and Timers
ocm ocm
0xF800C000 On-Chip Memory Registers
qspi qspi
0xE000D000 LQSPI module Registers
sd0 sdio
0xE0100000 SD2.0/ SDIO2.0/ MMC3.31 AHB Host
ControllerRegisters
sd1 sdio
0xE0101000 SD2.0/ SDIO2.0/ MMC3.31 AHB Host
ControllerRegisters
slcr slcr
0xF8000000 System Level Control Registers
smcc pl353
0xE000E000 Shared memory controller
spi0 SPI
0xE0006000 Serial Peripheral Interface
spi1 SPI
0xE0007000 Serial Peripheral Interface
swdt swdt
0xF8005000 System Watchdog Timer Registers
ttc0 ttc
0xF8001000 Triple Timer Counter
ttc1 ttc
0xF8002000 Triple Timer Counter
uart0 UART
0xE0000000 Universal Asynchronous Receiver Transmitter
uart1 UART
0xE0001000 Universal Asynchronous Receiver Transmitter
usb0 usb
0xE0002000 USB controller registers
usb1 usb
0xE0003000 USB controller registers
Module Name Module Type Base Address Description