User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 83
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
Domains
A domain is a collection of memory regions. Domains are only valid for L1 page table entries. The L1
page table entry format supports 16 domains, and requires the software that defines a translation
table to assign each memory region to a domain. The domain field specifies which of the 16 domains
the entry is in, and a two-bit field in the Domain Access Control register (DACR) defines the
permitted access for each domain. The possible settings for each domain are:
• No access – Any access using the translation table descriptor generates a Domain fault.
• Clients – On an access using the translation table descriptor, the access permission attributes
are checked. Therefore, the access might generate a permission fault.
• Managers – On an access using the translation table descriptor, the access permission attributes
are not checked. Therefore, the access cannot generate a Permission fault.
Shareable bit (S)
This bit determines whether the translation is for sharable memory. S = 0, the memory location is
non-shareable, and S = 1, it is sharable. For more information, refer to shareable attributes in section
3.2.4 Memory Ordering.
Non-Global Region Bit (nG)
The nG bit in the translation table entry permits the virtual memory map to be divided into global
and non-global regions. Each non-global region (nG = 1) has an associated address space identifier
(ASID), which is a number assigned by the OS to each individual task. If the nG bit is set for a
particular page, that page is associated with a specific application and is not global. This means that
when the MMU performs a translation, it uses both the virtual address and an ASID values. When a
page table walk occurs and the TLB is updated and the entry is marked as non-global, the ASID value
is stored in the TLB entry in addition to the normal translation information. Subsequent TLB look-ups
only match on that entry if the current ASID matches with the ASID that is stored in the entry. This
means you can have multiple valid TLB entries for a particular page (marked as non-global), but with
different ASID values. This significantly reduces the software overhead of context switches, as it
avoids the need to flush the on-chip TLBs.
Execute Never bit (xN)
When a memory location is marked as Execute Never (its XN attribute is set to 1) in a Client domain,
instructions are not allowed to fetch/prefetch. Any region of memory that is read-sensitive must be
marked as Execute Never to avoid the possibility of a speculative prefetch accessing the memory
region. For example, any memory region that corresponds to a read-sensitive peripheral must be
marked as Execute Never.
TLB Organization
The Cortex-A9 MMU includes two levels of TLBs which include a unified TLB for both instruction and
data and separate micro TLBs for each. The micro TLBs act as the first level TLBs and each have 32
fully associative entries. If an instruction fetch or a load/store address misses in the corresponding
micro TLB, the unified or main TLB is accessed. The unified main TLB provides a 2-way associative
2x64 entry table (128 entries) and supports four lockable entries using the lock-by-entry model. The