User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 837
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
DLL_calib 0x00000058 17 rw 0x00000101 DLL calibration
ODT_delay_hold
0x0000005C 16 rw 0x00000023 ODT delay and ODT hold
ctrl_reg1
0x00000060 13 mixed 0x0000003E Controller 1
ctrl_reg2
0x00000064 18 mixed 0x00020000 Controller 2
ctrl_reg3
0x00000068 26 rw 0x00284027 Controller 3
ctrl_reg4
0x0000006C 16 rw 0x00001610 Controller 4
ctrl_reg5
0x00000078 32 mixed 0x00455111 Controller register 5
ctrl_reg6
0x0000007C 32 mixed 0x00032222 Controller register 6
CHE_REFRESH_TIME
R01
0x000000A0 24 rw 0x00008000 CHE_REFRESH_TIMER01
CHE_T_ZQ
0x000000A4 32 rw 0x10300802 ZQ parameters
CHE_T_ZQ_Short_Inte
rval_Reg
0x000000A8 28 rw 0x0020003A Misc parameters
deep_pwrdwn_reg
0x000000AC 9 rw 0x00000000 Deep powerdown (LPDDR2)
reg_2c
0x000000B0 29 mixed 0x00000000 Training control
reg_2d
0x000000B4 11 rw 0x00000200 Misc Debug
dfi_timing
0x000000B8 25 rw 0x00200067 DFI timing
CHE_ECC_CONTROL
_REG_OFFSET
0x000000C4 2 rw 0x00000000 ECC error clear
CHE_CORR_ECC_LO
G_REG_OFFSET
0x000000C8 8 mixed 0x00000000 ECC error correction
CHE_CORR_ECC_AD
DR_REG_OFFSET
0x000000CC 31 ro 0x00000000 ECC error correction address log
CHE_CORR_ECC_DA
TA_31_0_REG_OFFSE
T
0x000000D0 32 ro 0x00000000 ECC error correction data log
low
CHE_CORR_ECC_DA
TA_63_32_REG_OFFSE
T
0x000000D4 32 ro 0x00000000 ECC error correction data log
mid
CHE_CORR_ECC_DA
TA_71_64_REG_OFFSE
T
0x000000D8 8 ro 0x00000000 ECC error correction data log
high
CHE_UNCORR_ECC_
LOG_REG_OFFSET
0x000000DC 1 clron
wr
0x00000000 ECC unrecoverable error status
CHE_UNCORR_ECC_
ADDR_REG_OFFSET
0x000000E0 31 ro 0x00000000 ECC unrecoverable error
address
CHE_UNCORR_ECC_
DATA_31_0_REG_OFF
SET
0x000000E4 32 ro 0x00000000 ECC unrecoverable error data
low
Register Name Address Width Type Reset Value Description