User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 84
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
TLB uses a pseudo round-robin replacement policy to determine which entry in the TLB should be
replaced in the case of a miss.
Unlike some other RISC processors that require software to manage the updates of the TLB from the
page table that resides in the memory, the main TLB in Cortex-A9 supports hardware page table
walks to perform look-ups in the L1 data cache. This allows the page tables to be cached.
The MMU can be configured to perform hardware translation table walks in cacheable regions by
setting the IRGN bits in the Translation Table Base registers. If the encoding of the IRGN bits is
write-back, then an L1 data cache look-up is performed and data is read from the data cache. If the
encoding of the IRGN bits is write-through or non-cacheable, then an access to external memory is
performed.
TLB entries can be global, or can be assigned to particular processes or applications using the ASIDs
associated with those processes. ASIDs enable TLB entries remain resident during context switches,
avoiding the requirement of reloading them subsequently.
Note: The ARM Linux kernel manages the 8-bit TLB ASID space globally across all CPUs instead of on
a per-CPU basis. The ASID is incremented for each new process. When the ASID rolls over (ASID = 0)
a TLB flush request is sent to both CPUs. However, only the CPU that is in the middle of a context
switch immediately updates its current ASID context. The other CPU continues to run using its
current pre-rollover ASID until a scheduling interval occurs and then it context switches to a new
process.
TLB maintenance and configuration operations are controlled through a dedicated coprocessor,
CP15, integrated within the core. This coprocessor provides a standard mechanism for configuring
the level one memory system.
Micro TLB
The first level of caching for the page table information is a micro TLB of 32 entries implemented on
each of the instruction and data sides. These blocks provide a fully associative look-up of the virtual
addresses in a cycle.
The micro TLB returns the physical address to the cache for the address comparison, and also checks
the protection attributes to signal either a pre-fetch abort or a data abort.
All main TLB related operations affect both the instruction and data micro TLBs, causing them to be
flushed. In the same way, any change of the Context ID register causes the micro TLBs to be flushed.
The main or unified TLB, explained in the next section, should be invalidated after a CPU reset and
before the MMU is enabled.
Main TLB
The main TLB is the second layer in the TLB structure that catches the misses from the Micro TLBs. It
also provides a centralized source for lockable translation entries.
Misses from the instruction and data micro TLBs are handled by a unified main TLB. Accesses to the
main TLB take a variable number of cycles, according to competing requests from each of the micro
TLBs and other implementation-dependent factors.