User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 85
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
Entries in the lockable region of the main TLB are lockable at the granularity of a single entry. As long
as the lockable region does not contain any locked entries, it can be allocated with non-locked
entries to increase overall main TLB storage size.
Translation Table Base Register 0 and 1
When managing multiple applications with their individual page tables, there is a need to have
multiple copies of the L1 page table, one for each application. Each of these are 16 KB in size. Most
of the entries are identical in each of the tables, as typically only one region of memory is
task-specific, with the kernel space being unchanged in each case. Furthermore, if there is a need to
modify a global page table entry, the change is needed in each of the tables.
To help reduce the effect of these problems, a second page table base register can be used. CP15
contains two page table base registers, TTBR0 and TTBR1. A control register (the TTB Control
register) is used to program a value in the range 0 to 7. This value (denoted by N) tells the MMU how
many upper bits of the virtual address it should check to determine which of the two TTB registers to
use. When N is 0 (the default), all virtual addresses are mapped using TTBR0. With N in the range 1-7,
the hardware looks at the most significant bits of the virtual address. If the N most significant bits
are all zero, TTBR0 is used, otherwise TTBR1 is used.
TTBR0 is used typically for process-specific addresses. On a context switch, TTBR0 is updated to
point to the first-level translation table for the new context and TTBCR is updated if this change
changes the size of the translation table. This table ranges in size from 128 bytes to 16 KB.
TTBR1 is used for operating system and I/O addresses that do not change on a context switch. The
size of this table is always 16 KB.
TLB Match Process
Each TLB entry contains a virtual address, a page size, a physical address, and a set of memory
properties. Each is marked as being associated with a particular application space, or as global for all
application spaces. A TLB entry matches if bits [31: N] of the modified virtual address (MVA) match,
where N is log2 of the page size for the TLB entry. It is either marked as global, or the ASID matched
the current ASID.
A TLB entry matches when these conditions are true:
• Its virtual address matches that of the requested address.
• Its non-secure TLB ID (NSTID) matches the secure or non-secure state of the MMU request.
• Its ASID matches the current ASID or is global.
The operating system must ensure that, at most, one TLB entry matches at any time. A TLB can store
entries based on the following block sizes:
Supersections: 16 MB blocks of memory
Sections:1MB blocks of memory
Large pages: 64 KB blocks of memory
Small pages:4KB blocks of memory