User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 860
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
Register DRAM_addr_map_row Details
Note: address bits are relative to a byte address. For example, the value 0x0FFF6666 selects byte address
bits [29:15] as row ddress bits in a 32-bit bus width configuration.
Register (ddrc) DRAM_ODT_reg
Field Name Bits Type Reset Value Description
reg_ddrc_addrmap_ro
w_b15
27:24 rw 0xF Selects the AXI address bit used as row address
bit 15. Valid Range: 0 to 5, Internal Base: 24 The
selected address bit is determined by adding the
Internal Base to the value of this field. If set to 15,
row address bit 15 is set to 0.
reg_ddrc_addrmap_ro
w_b14
23:20 rw 0xF Selects the AXI
address bit used as row address bit 14. Valid
Range: 0 to 6, Internal Base: 23 The selected
address bit is determined by adding the Internal
Base to the value of this field. If set to 15, row
address bit 14 is set to 0.
reg_ddrc_addrmap_ro
w_b13
19:16 rw 0x5 Selects the AXI address bit used as row address
bit 13. Valid Range: 0 to 7, Internal Base: 22 The
selected address bit is determined by adding the
Internal Base to the value of this field. If set to 15,
row address bit 13 is set to 0.
reg_ddrc_addrmap_ro
w_b12
15:12 rw 0x5 Selects the AXI address bit used as row address
bit 12. Valid Range: 0 to 8, Internal Base: 21 The
selected address bit is determined by adding the
Internal Base to the value of this field. If set to 15,
row address bit 12 is set to 0.
reg_ddrc_addrmap_ro
w_b2_11
11:8 rw 0x5 Selects the AXI address bits used as row address
bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11
(for row address bit 2) to 20 (for row address bit
11) The selected address bit for each of the row
address bits is determined by adding the Internal
Base to the value of this field.
reg_ddrc_addrmap_ro
w_b1
7:4 rw 0x5 Selects the AXI address bits used as row address
bit 1. Valid Range: 0 to 11. Internal Base: 10 The
selected address bit for each of the row address
bits is determined by adding the Internal Base to
the value of this field.
reg_ddrc_addrmap_ro
w_b0
3:0 rw 0x5 Selects the AXI address bits used as row address
bit 0. Valid Range: 0 to 11. Internal Base: 9
The selected address bit for each of the row
address bits is determined by adding the Internal
Base to the value of this field
Name DRAM_ODT_reg
Relative Address 0x00000048