User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 876
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
Register (ddrc) reg_2d
ddrc_reg_trdlvl_max_e
rror
25 ro 0x0 DDR2: not applicable.
LPDDR2 and DDR3: When '1' indicates that the
reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed
out. This is a Clear-on-Write register. If read
leveling or gate training timed out, an error is
indicated by the DDRC and this bit gets set. The
value is held at that value until it is cleared.
Clearing is done by writing a '0' to this register.
ddrc_reg_twrlvl_max_
error
24 ro 0x0 When '1' indicates that the
reg_ddrc_dfi_wrlvl_max_x1024 timer has timed
out. This is a Clear-on-Write register. If write
leveling timed out, an error is indicated by the
DDRC and this bit gets set. The value is held until
it is cleared.
Clearing is done by writing a '0' to this register.
Only present in designs that support DDR3.
dfi_rdlvl_max_x1024 23:12 rw 0x0 Read leveling maximum time.
Specifies the maximum number of clock cycles
that the controller will wait for a response
(phy_dfi_rdlvl_resp) to a read leveling enable
signal (ddrc_dfi_rdlvl_en or
ddrc_dfi_rdlvl_gate_en). Only applicable when
connecting to PHY's operating in 'PHY RdLvl
Evaluation' mode. Typical value 0xFFF Units 1024
clocks
dfi_wrlvl_max_x1024 11:0 rw 0x0 Write leveling maximum time. Specifies the
maximum number of clock cycles that the
controller will wait for a response
(phy_dfi_wrlvl_resp) to a write leveling enable
signal (ddrc_dfi_wrlvl_en). Only applicable when
connecting to PHY's operating in 'PHY WrLvl
Evaluation' mode. Typical value 0xFFF Units 1024
clocks
Name reg_2d
Relative Address 0x000000B4
Absolute Address 0xF80060B4
Width 11 bits
Access Type rw
Reset Value 0x00000200
Description Misc Debug
Field Name Bits Type Reset Value Description