User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 89
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
Debug and Trace Interfaces
Each Cortex-A9 processor has a standard 32-bit APB slave port that operates at the CPU_1x clock
frequency and is accessed through the debug APB bus master in the SOC debug block. The operation
of this block is explained in the corresponding chapter of this document.
The Cortex-A9 processors also include a pair of interfaces for trace generation and cross trigger
control. The trace source interface from each core is a 32-bit CoreSight standard ATB master port
that operates at the speed of the PS interconnect (CPU_2x clock), and is connected to the funnel in
the SOC debug block. Each core also has a 4-bit standard CoreSight cross trigger interface that
operates at the interconnect frequency (CPU_2x clock) and is connected to the cross trigger matrix
(CTM) in the SOC debug block.
Other Interfaces
Each Cortex-A9 processor has multiple control bits that are driven through the System-Level Control
register (SLCR). This includes a 4-bit interface that drives the CoreSight standard security signals and
also static configuration signals for controlling CP15 and SW programmability.
There are also other interfaces including the event and interrupt interfaces that are explained later in
this chapter.
3.2.7 NEON
• The Cortex-A9 NEON MPE extends the Cortex-A9 functionality to provide support for the ARM
v7 advanced SIMD and vector floating-point v3 (VFPv3) instruction sets. The Cortex-A9 NEON
MPE supports all addressing modes and data processing operations described in the ARM
Architecture Reference Manual.
The Cortex-A9 NEON MPE features are:
• SIMD vector and scalar single-precision floating-point computation
°
Unsigned and signed integers
°
Single bit coefficient polynomials
°
Single-precision floating-point values
• The operations supported by the NEON co-processor include:
°
Addition and subtraction
°
Multiplication with optional accumulation
°
Maximum or minimum value driven lane selection operations
°
Inverse square-root approximation
°
Comprehensive data-structure load instructions, including register-bank-resident table
lookup.
• Scalar double-precision floating-point computation
• SIMD and scalar half-precision floating-point conversion
• 8, 16, 32, and 64-bit signed and unsigned integer SIMD computation