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Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 896
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
The fifo_we_slave ratios for each slice(0 through 3) must be interpreted by software in the following way:
Slice 0: fifo_we_ratio_slice_0[10:0] = {Reg_6A[9],Reg_69[18:9]}
Slice1: fifo_we_ratio_slice_1[10:0] = {Reg_6B[10:9],Reg_6A[18:10]}
Slice2: fifo_we_ratio_slice_2[10:0] = {Reg_6C[11:9],Reg_6B[18:11]}
Slice3: fifo_we_ratio_slice_3[10:0] = {phy_reg_rdlvl_fifowein_ratio_slice3_msb,Reg_6C[18:12]}
Register (ddrc) reg69_6a0
Register reg69_6a0 Details
Register (ddrc) reg69_6a1
reg_phy_rd_rl_delay 9:5 rw 0x0 This delay determines when to select the active
rank's ratio logic delay for Read Data and Read
DQS slave delay lines after PHY receives a read
command at Control Interface.
The programmed value must be (Read Latency -
3) with a minimum value of 1.
reg_phy_wr_rl_delay 4:0 rw 0x0 This delay determines when to select the active
rank's ratio logic delay for Write Data and Write
DQS slave delay lines after PHY receives a write
command at Control Interface.
The programmed value must be (Write Latency -
4) with a minimum value of 1.
Field Name Bits Type Reset Value Description
Name reg69_6a0
Relative Address 0x000001A4
Absolute Address 0xF80061A4
Width 29 bits
Access Type ro
Reset Value 0x00070000
Description Training results for data slice 0.
Field Name Bits Type Reset Value Description
phy_reg_status_fifo_w
e_slave_dll_value
27:19 ro 0x0 Delay value applied to FIFO WE slave DLL.
phy_reg_rdlvl_fifowei
n_ratio
18:9 ro 0x380 Ratio value generated by Read Gate training FSM.
reserved 8:0 ro 0x0 Reserved. Do not modify.
Name reg69_6a1