User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 92
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
3.4 L2-Cache
3.4.1 Summary
The L2 cache controller is based on the ARM PL310 and includes an 8-way set-associative 512 KB
cache for dual/single Cortex-A9 cores. The L2 cache is physically addressed and physically tagged
and supports a fixed 32-byte line size. These are the main features of the L2 cache:
• Supports snoop coherency control utilizing MESI algorithm.
• Offers parity check for L2 cache memory.
• Supports speculative read operations in the SMP mode.
• Provides L1/L2 exclusive mode (that is, data exists in either, but not both).
• Can be locked down by master, line, or way per master.
• Implements 16-entry deep preload engine for loading data into L2 cache memory.
• To improve latency, critical-word-first line-fill is supported.
• Implements pseudo-random victim selection policy with deterministic option.
°
Write-through and write-back.
°
Read allocate, write allocate, read and write allocate.
• The contents of the L2 data and tag RAMs are cleared upon an L2 reset to comply with security
requirements.
• The L2 controller implements multiple 256-bit line buffers to improve cache efficiency.
°
Line fill buffers (LFBs) for external memory access to create a complete cache line into L2
cache memory. Four LFBs are implemented for AXI read interleaving support.
°
Two 256-bit line read buffers for each slave port. These buffers hold a line from the L2 cache
in case of cache hit.
°
Three 256-bit eviction buffers hold evicted lines from the L2 cache, to be written back to
main memory.
°
Three 256-bit store buffers hold bufferable writes before their draining to main memory, or
L2 cache. They enable multiple writes to the same line to be merged.
• The controller implements selectable cache pre-fetching within 4k boundaries.
• The L2 cache controller forwards exclusive requests from L1 to DDR, OCM, or external memory.
Note: The SCU does not maintain coherency between instruction and data L1 caches, so this
coherency must be maintained by software.
The L2 cache implements TrustZone security extension to offer enhanced OS security. The
non-secure (NS) tag bit is added in tag RAM and is used for lookup in the same way as an address bit.
The NS tag bit is also added in all of the buffers. The NS bit in tag RAM is used to determine the
security level of evictions to DDR and OCM. The controller restricts non-secure accesses for control,
configuration, and maintenance registers to restrict access to secure data.