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Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 95
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
3.4.2 Exclusive L2-L1 Cache Configuration
In the exclusive cache configuration mode, the L1 data cache of the Cortex-A9 processor and the L2
cache are exclusive. At any time, a given address is cached in either L1 data cache or in the L2 cache,
but not in both. This has the effect of increasing the usable space and efficiency of the L2 cache.
When exclusive cache configuration is selected:
• Data cache line replacement policy is modified so that the victim line in the L1 always gets
evicted to the L2, even if it is clean.
• If a line is dirty in the L2 cache, a read request to this address from the processor causes
write-back to external memory and a line-fill to the processor.
Both L1 and L2 caches have to be configured for exclusive caching. Setting the exclusive cache
configuration bit 12 in the auxiliary control register for L2 and bit 7 of the ACTLR register in
Cortex-A9 configure the L2 and L1 caches to operate exclusive to one another.
For reads, the behavior is as follows:
• For a hit, the line is marked as non-valid (the tag RAM valid bit is reset) and the dirty bit is
unchanged. If the dirty bit is set, future accesses can still hit in this cache line, but the line is part
of the preferred choice for future evictions.
• For a miss, the line is not allocated into the L2 cache.
For writes, the behavior depends on the value of attributes from the SCU to indicate if the write
transaction is an eviction from the L1 memory system and whether it is a clean eviction. AWUSERS[8]
attribute indicates an eviction and AWUSERS[9] indicates a clean eviction. The behavior is
summarized as follows:
• For a hit, the line is marked dirty unless the AWUSERS[9:8] = b11. In this case, the dirty bit is
unchanged.
Cacheable
write-through,
allocate on read
and write
Outer
write-through,
allocate on both
reads and writes
• Read hit: Read from L2.
• Read miss: Line fill to L2.
• Write hit: Put in store buffer, write to L2 and memory when store
buffer is drained.
• Write miss: Put in store buffer. When buffer has to be drained, check
whether it is full. If it is not full then request word or line to memory
before allocating the buffer to the L2. Allocation to L2. Write to
memory.
Cacheable
write-back,
allocate on read
and write
Outer write-back,
write allocate
• Read hit: Read from L2.
• Read miss: Line fill to L2.
• Write hit: Put in store buffer, write to L2 when store buffer is drained,
and mark line as dirty.
• Write miss: Put in store buffer. When buffer has to be drained, check
if it is full. If it is not full then request word or line to memory before
allocating the buffer to L2. Allocation to L2.
Table 3-5: Cache Controller Behavior for SCU Requests (Cont’d)
Transaction Type ARMv7 Equivalent L2 Cache Controller Behavior