User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 954
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
ETMACTR3 0x00000088 12 mixed 0x00000001 Address Comparator Access
Type Register 3
ETMACTR4
0x0000008C 12 mixed 0x00000001 Address Comparator Access
Type Register 4
ETMACTR5
0x00000090 12 mixed 0x00000001 Address Comparator Access
Type Register 5
ETMACTR6
0x00000094 12 mixed 0x00000001 Address Comparator Access
Type Register 6
ETMACTR7
0x00000098 12 mixed 0x00000001 Address Comparator Access
Type Register 7
ETMACTR8
0x0000009C 12 mixed 0x00000001 Address Comparator Access
Type Register 8
ETMCNTRLDVR1
0x00000140 16 rw 0x00000000 Counter Reload Value Register 1
ETMCNTRLDVR2
0x00000144 16 rw 0x00000000 Counter Reload Value Register 2
ETMCNTENR1
0x00000150 18 mixed 0x00020000 Counter Enable Event Register 1
ETMCNTENR2
0x00000154 18 mixed 0x00020000 Counter Enable Event Register 2
ETMCNTRLDEVR1
0x00000160 17 rw 0x00000000 Counter Reload Event Register 1
ETMCNTRLDEVR2
0x00000164 17 rw 0x00000000 Counter Reload Event Register 2
ETMCNTVR1
0x00000170 16 rw 0x00000000 Counter Value Register 1
ETMCNTVR2
0x00000174 16 rw 0x00000000 Counter Value Register 2
ETMSQ12EVR
0x00000180 17 rw 0x00000000 Sequencer State Transition
Event Register 12
ETMSQ21EVR
0x00000184 17 rw 0x00000000 Sequencer State Transition
Event Register 21
ETMSQ23EVR
0x00000188 17 rw 0x00000000 Sequencer State Transition
Event Register 23
ETMSQ31EVR
0x0000018C 17 rw 0x00000000 Sequencer State Transition
Event Register 31
ETMSQ32EVR
0x00000190 17 rw 0x00000000 Sequencer State Transition
Event Register 32
ETMSQ13EVR
0x00000194 17 rw 0x00000000 Sequencer State Transition
Event Register 13
ETMSQR
0x0000019C 2 rw 0x00000000 Current Sequencer State
Register
ETMEXTOUTEVR1
0x000001A0 17 rw 0x00000000 External Output Event Register
1
ETMEXTOUTEVR2
0x000001A4 17 rw 0x00000000 External Output Event Register
2
ETMCIDCVR1
0x000001B0 32 rw 0x00000000 Context ID Comparator Value
Register
Register Name Address Width Type Reset Value Description