User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 96
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
• For a miss, if the cache line is evicted (AWUSERS[8] is 1), the cache line is allocated and its dirty
status depends on if it is evicted dirty or not. If the cache line is evicted dirty (AWUSERS[8] is 0),
the cache line is allocated only if it is write allocate.
3.4.3 Cache Replacement Strategy
Bit [25] of the Auxiliary Control register configures the replacement strategy. It can be either
round-robin or pseudo-random. The round-robin replacement strategy fills invalid and unlocked
ways first; for each line, when ways are all valid or locked, the victim is chosen as the next unlocked
way. The pseudo-random replacement strategy fills invalid and unlocked ways first; for each line,
when ways are all valid or locked, the victim is chosen randomly between unlocked ways.
When a deterministic replacement strategy is required, the lockdown registers are used to prevent
ways from being allocated. For example, since L2 cache is 512 KB and is 8-way set-associative, each
way is 64 KB. If a piece of code is required to reside in two ways (128 KB), with a deterministic
replacement strategy, ways 1-7 must be locked before the code is filled into the L2 cache. If the first
64 KB of code is allocated into way 0 only, then way 0 must be locked and way 1 unlocked so that the
second half of the code can be allocated in way 1.
There are two lockdown registers, one for data and one for instructions. If required, one can separate
data and instructions into separate ways of the L2 cache.
3.4.4 Cache Lockdown
The L2 cache controller allows locking down entries by line, by way, or by master (includes both CPU
and ACP masters.) Lockdown by line and lockdown by way can be used at the same time; lockdown
by line and lockdown by master can also be used at the same time. However, lockdown by master
and lockdown by way are exclusive, because lockdown by way is a subset of lockdown by master.
Lockdown by Line
When enabled, all newly allocated cache lines get marked as locked. The controller then considers
them as locked and does not naturally evict them. It is enabled by setting bit [0] of the lockdown by
the line enable register. Bit [21] of the tag RAM shows the locked status of each cache line.
TIP: An example of when the lockdown by line feature might be enabled is during the time when a
critical piece of software code is loaded into the L2 cache.
The unlock all lines background operation enables the unlocking of all lines marked as locked by the
lockdown by line mechanism. The status of this operation can be checked by reading the unlock all
lines register. While an unlock all lines operation is in progress, you cannot launch a background
cache maintenance operation. If attempted, a SLVERR error is returned.
Lockdown by Way
The L2 cache is 8-way set-associative and allows users to lock the replacement algorithm on a way
basis, enabling the set count to be reduced from 8-way all the way down to direct mapped. The