User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 98
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
3.4.5 Enabling and Disabling the L2 Cache Controller
The L2 cache is disabled by default and can be enabled by setting bit 0 of the L2 cache control
register independently of the L1 caches. When the cache controller block is not enabled, depending
on their addresses, transactions pass through to the DDR memory or the main interconnect on the
cache controller master ports. The address latency introduced by the disabled cache controller is one
cycle in the slave port from the SCU plus one cycle in the master ports.
3.4.6 RAM Access Latency Control
The L2 cache data and tag RAMs use the same clock as the Cortex-A9 processors; however, it is not
feasible to access these RAMs in a single cycle when the clock runs at its maximum speed. To address
this issue, the L2-cache controller provides a mechanism to adjust the latencies for the write access,
read access, and setup of both RAM arrays by respectively setting bits [10:8], [6:4], and [2:0] of its tag
RAM and data RAM latency control registers. The default value for these fields is 3'b111 for both
registers, which corresponds to the maximum latency of eight CPU_6x4x cycles for the three
attributes of each RAM array. Because these large latencies result in very poor cache performance,
the software should program the attributes as follows:
• Set the latencies for the three tag RAM attributes to 2 by writing 3'b001 to bits [10:8], [6:4],
and [2:0] of the tag RAM latency control register.
• Set the latencies for the write access and setup of the data RAM to 2 by writing 3'b001 to bits
[10:8] and [2:0] of the data RAM latency control register.
• Set the read access latency of the data RAM to 3 by writing 3'b010 to bits [6:4] of the data RAM
latency control register.
3.4.7 Store Buffer Operation
Two buffered write accesses to the same address and the same security bit cause the first write
access to be overridden if the controller does not drain the store buffer after the first access. The
store buffer has merging capabilities, so it merges successive writes to the same line address into the
same buffer slot. This means that the controller does not drain the slots as soon as they contain data,
but rather waits for other potential accesses that target the same cache line. The store buffer
draining policy is as follows. Slave port refers to the port from the SCU to the L2 cache controller:
• The store buffer slot is immediately drained if targeting device memory area.
• The store buffer slots are drained as soon as they are full.
• The store buffer is drained at each strongly-ordered read occurrence in the slave port.
• The store buffer is drained at each strongly ordered write occurrence in the slave port.
• If the three slots of the store buffer contain data, the least recently accessed slot is drained.
• If a hazard is detected with one store buffer slot, it is drained to resolve the hazard. Hazards can
occur when data is present in the cache buffers, but not yet present in the cache RAM or
external memory.
• The store buffer slots are drained when a locked transaction is received by the slave port.
• The store buffer slots are drained when a transaction targeting the configuration registers is
received by the slave port.