User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 99
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
Merging condition is based on address and security attribute. Merging takes place only when data is
in the store buffer and it is not draining.
When a write-allocate cacheable slot is drained, misses in the cache, and is not full, the store buffer
sends a request through the master ports to the main interconnects or DDR to complete the cache
line. The corresponding master port sends a read request through the interconnects and provides
data to the store buffer in return. When the slot is full, it can be allocated into the cache.
3.4.8 Optimizations Between Cortex-A9 and L2 Controller
To improve performance, the SCU interface to the L2 controller, and partially the interface to the
on-chip memory controller (OCM), implement several optimizations:
• Early write response
•Pre-fetch hints
• Full line of zero write
• Speculative reads of the Cortex-A9 MPCore processor
These optimizations apply to the transfers from the processor and do not include the ACP.
Early Write Response
During the write transaction from the Cortex-A9 to the L2 cache controller, the write response from
the L2 controller is normally returned to the SCU only when the last data beat has arrived at the L2
controller. This optimization enables the L2 controller to send the write response of certain write
transactions as soon as the store buffer accepts the write address and allows the Cortex-A9
processor to provide a higher bandwidth for writes. This feature is disabled by default and you can
enable it by setting the Early BRESP enable bit in the auxiliary control register for the L2 controller.
The Cortex-A9 does not require any programming to enable this feature. OCM does not support this
feature and its write responses are generated normally.
Pre-fetch Hints
When the Cortex-A9 processor is configured to run in SMP mode, the automatic data pre-fetchers
implemented in the CPUs issue special read accesses to the L2 cache controller. These special reads
are called pre-fetch hints. When the L2 controller receives such pre-fetch hints, it allocates the
targeted cache line into the L2 cache for a miss without returning any data back to the Cortex-A9
processor. You can enable the pre-fetch hint generation by the Cortex-A9 processors through one of
the two following methods:
1. Enabling the L2 pre-fetch hint feature by setting bit [1] of the ACTLR register. When enabled, this
feature sets the Cortex-A9 processor to automatically issue L2 pre-fetch hint requests when it
detects regular fetch patterns on a coherent memory.
2. Use of PLE (pre-load engine) operations. When this feature is used in the Cortex-A9 processor,
the PLE issues a series of L2 pre-fetch hint requests at the programmed addresses.