Datasheet

Digilent Pmod™ Interface Specification 1.2.0
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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RESET - Reset signal for master to reset slave
CS2 - Chip Select 2. Active low to enable second slave device
CS3 - Chip Select 3. Active low to enable third slave device
5.3 UART
Pmod Interface Type 3 (UART)
This provides a UART interface with optional hardware flow control. When this interface is placed on a twelve-pin
connector on a host, pins 1-6 should be used (i.e. the upper row of pins). The hardware flow control signals are
optional, and some Pmods do not use them. In this case pins 1 & 4 are either not used or are GPIO.
The hardware flow control signal names are defined from the system board perspective. The RTS signal is an
output indicating that the device (host or peripheral) is ready to receive data. The device asserts this signal low
when it is ready to receive data. The CTS signal is an input to the device (host or peripheral). The device will only
transmit data when the CTS input is asserted low. A peripheral module that uses hardware flow control will
connect the host’s RTS signal to its internal CTS input and the host’s CTS signal to its internal RTS output.
Pin
Signal
Direction
Alternate Signal
Direction
1
CTS
In
GPIO
In/Out
2
TXD
Out
-
-
3
RXD
In
-
-
4
RTS
Out
GPIO
In/Out
5
GND
GND
6
VCC
VCC
CTS - Host is clear to send (will only transmit when this signal is asserted)
RTS - Host request to send
RXD - Data from peripheral to host
TXD - Data from host to peripheral
Pmod Interface Type 3A (expanded UART)
This provides a UART interface with optional hardware flow control plus additional control signals. The hardware
flow control signals are optional, and some Pmods do not use them. In this case pins 1 & 4 are not used or are
GPIO. Pins 7-10 can be any signal, but if one or more interrupts are needed they will be on pin 7 and if a reset is
needed it will be on pin 8.
The hardware flow control signal names are defined from the system board perspective. The RTS signal is an
output indicating that the device (host or peripheral) is ready to receive data. The device asserts this signal low
when it is ready to receive data. The CTS signal is an input to the device (host or peripheral). The device will only
transmit data when the CTS input is asserted low. A peripheral module that uses hardware flow control will
connect the host’s RTS signal to its internal CTS input and the host’s CTS signal to its internal RTS output.