Arty S7 Reference Manual The Arty S7 board features the new Xilinx Spartan-7 FPGA and is the latest member of the Arty FPGA development board family from Digilent. The Spartan-7 FPGA offers the most size, performance, and cost-conscious design engineered with the latest technologies from Xilinx and is fully compatible with Vivado Design Suite. Putting this FPGA in the Arty form factor provides users with a wide variety of I/O and expansion options.
Features Xilinx Spartan-7 50 FPGA (xc7s50csga324-1) o 8,150 slices (each slice contains four 6-input LUTs and 8 flip-flops) o 2,700 Kbits of fast block RAM o Five clock management tiles, each with a phase-locked loop (PLL) o 120 DSP slices o Internal clock speeds exceeding 450MHz o On-chip analog-to-digital converter (XADC) o Programmable over JTAG and Quad-SPI Flash Memory o 256MB DDR3L with a 16-bit bus @ 650MHz o 16MB Quad-SPI Flash Power o Powered from USB or any 7V-15V external power sou
CalloutDescription CalloutDescription 1 FPGA programming DONE LED 11 SPI header (Arduino/ChipKIT compatible) 2 Shared USB JTAG / UART port 12 Arduino IDE reset jumper 3 Power select jumper (Ext. supply / USB)13 FPGA programming mode (JTAG/ Flash) 4 Power jack (for optional ext.
Purchasing Options The board is sold standalone, but requires either a micro USB cable or 7-15V external power supply to be powered. The external power supply must have a coaxial, center-positive connector with 2.1 mm or 2.5 mm internal diameter. When purchased from Digilent, a micro USB cable or suitable 12V, 3A power supply can added at the time of purchase. You may see the Arty S7 referred to as the Arty S7-50 throughout some Digilent documentation.
Hardware Definition Language (HDL), specifically Verilog or VHDL. For those with no interest in learning HDL, the Xilinx High Level Synthesis tool can be used to define custom peripheral blocks by writing them in C. The Arty S7's Soft SoC configurations are powered by MicroBlaze processor cores. MicroBlaze is a 32-bit RISC soft processor core, designed specifically to be used in Xilinx FPGAs.
Functional Description 1 Power Supplies The Arty S7 board requires a 5 volt power source to operate. This power source can come from the Digilent USB-JTAG port (J10) or it can be derived from a 7 to 15 Volt DC power supply that’s connected to the Power Jack (J12) or Pin 8 of Header J7. Header JP13, labeled “5V SELECT”, is used to determine which source is used.
Figure 1.2. Arty S7 Battery Pack Connection. Voltage regulator circuits from Analog Devices and Texas Instruments create the required 3.3V, 1.8V, 1.35V, 1.25V, and 1.00V supplies from the 5V power source. In the event that an external supply or battery pack is used, the on-board Analog Devices 5V regulator provides the 5V source. Table 1.1 provides additional information (typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs).
Figure 2.1. Arty S7 FPGA Configuration. Figure 2.1 shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP1) selects whether the FPGA will be programmed by the Quad-SPI flash on power up. The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The Vivado software from Xilinx can create bitstreams from VHDL, Verilog®, or block-level design. Bitstreams are stored in volatile memory cells within the FPGA.
2.2 Quad-SPI Configuration Since the FPGA's memory on the Arty S7 is volatile, it relies on the Quad-SPI flash memory to store the configuration between power cycles. This configuration mode is called Master SPI. The blank FPGA takes the role of master and reads the configuration file out of the flash device upon power-up. To that effect, a configuration file needs to be downloaded first to the flash.
the design. It is also possible to generate the reference clock from the MIG itself by enabling “Select Additional Clocks” and generating a clock with a 5007 ps period (199.69231 MHz). This clock will be within spec for the reference clock requirements, and can be looped around back into the reference clock input of the MIG IP core. The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core.
5 Oscillators/Clocks The Arty S7 board includes a 12 MHz crystal oscillator connected to pin F14 (an MRCC input on bank 15) and a 100 MHz crystal oscillator connected to pin R2 (an MRCC input on bank 34). The 12 MHz clock is intended to be used as a general purpose system clock. The clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design.
Figure 6.1. UART Connections. 7 Basic I/O The Arty S7 board includes two tri-color LEDs, 4 switches, 4 push buttons, 4 individual LEDs, and a reset button, as shown in Figure 8.1. The push buttons and slide switches are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button or slide switch was inadvertently defined as an output).
Figure 7.1. Arty S7 GPIO. The four individual high-efficiency LEDs are anode-connected to the FPGA via 330-ohm resistors, so they will turn on when a logic high voltage is applied to their respective I/O pin. Additional LEDs that are not user-accessible indicate power-on, FPGA programming status, and USB and Ethernet port status. 7.1 Tri-Color LEDs The Arty S7 board contains two tri-color LEDs.
0% causes the different colors to be illuminated at different intensities, allowing virtually any color to be displayed. 8 Pmod Connectors Pmod connectors are 2×6, right-angle, 100-mil spaced female connectors that mate with standard 2×6 pin headers. Each 12-pin Pmod connector provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure 8.1.
8.2 High-Speed Pmod The High-speed Pmods use the standard Pmod connector, but have their data signals routed as impedance matched differential pairs for maximum switching speeds. They have pads for loading resistors for added protection, but the Arty S7 ships with these loaded as 0-Ohm shunts. With the series resistors shunted, these Pmods offer no protection against short circuits, but allow for much faster switching speeds.
Figure 9.1. Shield connector pin diagram.
Pin Name Shield Function Arty S7 Connection Differential See Section titled “Shield Analog I/O” Analog Input Dedicated V_P, V_N Differential See Section titled “Shield Analog I/O” Analog Input XADC Analog Connected to net used to drive the XADC ground XGND Ground reference on the FPGA (VREFN) XADC Analog Connected to 1.25 V, 25mA rail used to drive the XVREF Voltage XADC voltage reference on the FPGA (VREFP) Reference N/C Not Connected Not Connected Digital I/O Connected to the Arty S7 3.
Arty S7's GND) that is applied to any of these pins. If you wish to use the pins labeled A0-A5 as Digital inputs or outputs, they are also connected directly to the FPGA before the resistor divider circuit (also shown in Figure 9.2.1). Figure 9.2.1. Single-Ended Analog Inputs The pins labeled A6-A9 are connected directly to 2 pairs of analog capable pins on the FPGA via an anti-aliasing filter. This circuit is shown in Figure 9.2.2.
The XADC core within the Spartan-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA.
