Datasheet

the design. It is also possible to generate the reference clock from the MIG itself by enabling “Select
Additional Clocks” and generating a clock with a 5007 ps period (199.69231 MHz). This clock will
be within spec for the reference clock requirements, and can be looped around back into the
reference clock input of the MIG IP core.
The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated
before generating the IP core. For your convenience, an importable UCF file is provided on the
Arty S7 resource center to speed up this process. It is included in the digilent-mig repository on
the Digilent Github. This download also includes a .prj file that can be imported into the wizard to
automatically configure it with the options found in Table 3.1.
For those using the MIG with a MicroBlaze project, it is not necessary to use the files found in the
digilent-mig repository. Instead, the Arty S7 MIG settings and pinout will be automatically imported
from the Digilent Vivado board files.
For more details on the Xilinx MIG, refer to the 7 Series FPGAs Memory Interface Solutions User
Guide (ug586).
4 Quad-SPI Flash
FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number
S25FL128S), and setting the mode jumper will cause the FPGA to automatically read a
configuration from this device at power on. A Spartan-7 50T configuration file requires 17,536,096
bits of memory, leaving about 87% of the flash device (or ~13.92 MB) available for user data. A
common use for this extra memory is to store Microblaze programs too big to fit in the onboard
Block memory (typically 128 KB). These programs are then loaded and executed using a smaller
bootloader program that can fit in the block memory. It is possible to automatically generate this
bootloader, roll it into your bitstream, and then program the bitstream and large microblaze
program into the Quad SPI Flash using Xilinx SDK.
The contents of the memory can be manipulated by issuing certain commands on the SPI bus.
The implementation of this protocol is outside the scope of this document. Xilinx's AXI Quad SPI
core can be used to read/write the flash in a Microblaze design. Refer to Xilinx's product guide for
this core to learn more about using it, or to Spansion's datasheet for the flash device to learn how
to implement a custom controller.
All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration and can be
used like any other FPGA I/O, except for SCK. It can only be accessed by instantiating a special
primitive called STARTUPE2. The Xilinx AXI Quad SPI IP core has a configuration option that will
automatically instantiate the primitive for you, and this option should be enabled when using it with
the Arty S7. For information on instantiating the primitive from HDL, refer to the “Vivado Design
Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide” (UG953) from Xilinx.
Figure 4.1. Arty S7 SPI flash.