Datasheet
Pin Name
Shield Function
Arty S7 Connection
Shared
Connections
A6-A9
Differential
Analog Input
See Section titled “Shield Analog I/O”
–
V_P, V_N
Dedicated
Differential
Analog Input
See Section titled “Shield Analog I/O”
–
XGND
XADC Analog
Ground
Connected to net used to drive the XADC ground
reference on the FPGA (VREFN)
–
XVREF
XADC Analog
Voltage
Reference
Connected to 1.25 V, 25mA rail used to drive the
XADC voltage reference on the FPGA (VREFP)
–
N/C
Not Connected
Not Connected
–
IOREF
Digital I/O
Voltage reference
Connected to the Arty S7 3.3V Power Rail (See
the “Power Supplies” section)
–
RST
Reset to Shield
Connected to the red “RESET” button and a
Digital I/O of the FPGA. When JP2 is shorted, it
is also connected to the DTR signal of the FTDI
USB-UART bridge.
–
3V3
3.3V Power Rail
Connected to the Arty S7 3.3V Power Rail (See
the “Power Supplies” section)
–
5V0
5.0V Power Rail
Connected to the Arty S7 5.0V Power Rail (See
the “Power Supplies” section)
–
GND, G
Ground
Connected to the Ground plane of Arty S7
–
VIN
Power Input
Connected in parallel with the external power
supply connector (J12). See the “Power
Supplies” section for information on powering the
Arty S7 from this pin.
–
Table 9.1. Arty S7 Shield Pinout
9.1 Shield Digital I/O
The pins connected directly to the FPGA can be used as general purpose inputs or outputs. These
pins include the I2C, SPI, and general purpose I/O pins. There are 200 Ohm series resistors
between the FPGA and the digital I/O pins to help provide protection against accidental short
circuits (pins A10 and A11 instead have 140 Ohm series resistors). The absolute maximum and
recommended operating voltages for these pins are outlined in Table 9.1.1.
Absolute
Minimum
Voltage
Recommended
Minimum Operating
Voltage
Recommended
Maximum Operating
Voltage
Absolute
Maximum
Voltage
Powered
-0.4 V
-0.2 V
3.4 V
3.75 V
Unpowered
-0.4 V
N/A
N/A
0.55 V
Table 9.1.1. Shield Voltage Specifications
For more information on the electrical characteristics of the pins connected to the FPGA, please
see the Spartan-7 datasheet from Xilinx.
The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. When
using these signals to implement an I2C bus it is necessary to attach a pull-up resistor to them. On
the Arty S7, this can be done by placing two shorting blocks horizontally across the J4 header.
9.2 Shield Analog I/O
The pins labeled A0-A9 and V_P/V_N are used as analog inputs to the XADC module of the FPGA.
The FPGA expects that the inputs range from 0-1 V. On the pins labeled A0-A5 we use an external
circuit to scale down the input voltage from 3.3V. This circuit is shown in Figure 9.2.1. This circuit
allows the XADC module to accurately measure any voltage between 0V and 3.3V (relative to the