Datasheet

Figure 2.1. Arty S7 FPGA Configuration.
Figure 2.1 shows the different options available for configuring the FPGA. An on-board “mode”
jumper (JP1) selects whether the FPGA will be programmed by the Quad-SPI flash on power up.
The FPGA configuration data is stored in files called bitstreams that have the .bit file extension.
The Vivado software from Xilinx can create bitstreams from VHDL, Verilog®, or block-level design.
Bitstreams are stored in volatile memory cells within the FPGA. This data defines the FPGA’s logic
functions and circuit connections, and it remains valid until it is erased by removing board power,
by pressing the reset button attached to the PROG input, or by writing a new configuration file
using the JTAG port.
A Spartan-7 50T bitstream is typically 17,536,096 bits. The time it takes to program the Arty S7
can be decreased by compressing the bitstream before programming, and then allowing the FPGA
to decompress the bitstream itself during configuration. Depending on design complexity,
compression ratios of 10x can be achieved. Bitstream compression can be enabled within the
Xilinx tools to occur during generation. For instructions on how to do this, consult the Xilinx
documentation for the toolset being used.
After being successfully programmed, the FPGA will cause the “DONE” LED to illuminate. Pressing
the “PROG” button at any time will reset the configuration memory in the FPGA. After being reset,
if JP1 is set then the FPGA will immediately attempt to reprogram itself from Quad SPI flash.
The following sections provide greater detail about programming the Arty S7 using the different
methods available.
2.1 JTAG Configuration
The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan
Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred
from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J10) or an external
JTAG programmer, such as the Digilent JTAG-HS2, attached to port J9. You can perform JTAG
programming any time after the Arty S7 has been powered on, regardless of whether the mode
jumper (JP1) is set. If the FPGA is already configured, then the existing configuration is overwritten
with the bitstream being transmitted over JTAG. Not setting the mode jumper (seen in Figure 2.1)
is useful to prevent the FPGA from being configured from Quad-SPI Flash until a JTAG
programming occurs.
Programming the Arty S7 with an uncompressed bitstream using the on-board USB-JTAG circuitry
usually takes around 6 seconds. JTAG programming can be done using the hardware manager in
Vivado.