Data Sheet

3/15/2018 Arty S7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/arty-s7/reference-manual 12/22
(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-s7/arty-s7-config.png?id=reference%3Aprogrammable-logic%3Aarty-
s7%3Areference-manual) Figure 2.1. Arty S7 FPGA Configuration.
Figure 2.1 shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP1) selects whether the FPGA
will be programmed by the Quad-SPI flash on power up.
The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The Vivado software from Xilinx can create
bitstreams from VHDL, Verilog®, or block-level design.
Bitstreams are stored in volatile memory cells within the FPGA. This data defines the FPGA’s logic functions and circuit connections, and it
remains valid until it is erased by removing board power, by pressing the reset button attached to the PROG input, or by writing a new
configuration file using the JTAG port.
A Spartan-7 50T bitstream is typically 17,536,096 bits. The time it takes to program the Arty S7 can be decreased by compressing the
bitstream before programming, and then allowing the FPGA to decompress the bitstream itself during configuration. Depending on design
complexity, compression ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools to occur during
generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used.
After being successfully programmed, the FPGA will cause the “DONE” LED () to illuminate. Pressing the “PROG” button at any time
will reset the configuration memory in the FPGA. After being reset, if JP1 is set then the FPGA will immediately attempt to reprogram itself
from Quad SPI flash.
The following sections provide greater detail about programming the Arty S7 using the different methods available.
The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as
JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port
J10) or an external JTAG programmer, such as the Digilent JTAG-HS2, attached to port J9. You can perform JTAG programming any time
after the Arty S7 has been powered on, regardless of whether the mode jumper (JP1) is set. If the FPGA is already configured, then the
existing configuration is overwritten with the bitstream being transmitted over JTAG. Not setting the mode jumper (seen in Figure 2.1) is
useful to prevent the FPGA from being configured from Quad-SPI Flash until a JTAG programming occurs.
Programming the Arty S7 with an uncompressed bitstream using the on-board USB-JTAG circuitry usually takes around 6 seconds. JTAG
programming can be done using the hardware manager in Vivado.
Since the FPGA's memory on the Arty S7 is volatile, it relies on the Quad-SPI flash memory to store the configuration between power
cycles. This configuration mode is called Master SPI. The blank FPGA takes the role of master and reads the configuration file out of the
flash device upon power-up. To that effect, a configuration file needs to be downloaded first to the flash. When programming a non-volatile
flash device, a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a circuit that can program
flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx
tools). This is called indirect programming. After the flash device has been programmed, it can automatically configure the FPGA at a
subsequent power-on or reset event as determined by the mode jumper setting (see Figure 2.1). Programming files stored in the flash device
will remain until they are overwritten, regardless of power-cycle events.
Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory
technology. Once written however, FPGA configuration can be very fast—less than a second. Bitstream compression, SPI bus width, and
configuration rate are factors controlled by the Xilinx tools that can affect configuration speed. The Arty S7 supports x1, x2, and x4 bus
widths and data rates of up to 50 MHz () for Quad-SPI programming.
Quad-SPI programming can be done using the hardware manager in Vivado.
The Arty S7 includes one MT41K128M16JT-125 memory component, creating a single rank, 16-bit wide interface. It is routed to a 1.35V-
powered HR (High Range) FPGA bank with 50 ohm controlled single-ended trace impedance. 50 ohm internal terminations in the FPGA
are used to match the trace characteristics. Similarly, on the memory side, on-die terminations (ODT) are used for impedance matching.
For proper operation of the memory, a memory controller and physical layer (PHY) interface needs to be included in the FPGA design. The
easiest way to accomplish this on the Arty S7 is to use the Xilinx 7-series memory interface solutions core generated by the MIG (Memory
Interface Generator) Wizard. The MIG Wizard can generate a native FIFO-style or an AXI4 interface to connect to user logic. This
workflow allows the customization of several DDR parameters optimized for the particular application. Table 3.1 below lists the MIG
Wizard settings optimized for the Arty S7 (any settings not mentioned can be left in default state).
Setting Value
2.1 JTAG Configuration
2.2 Quad-SPI Configuration
3 DDR3L Memory