Data Sheet

3/15/2018 Arty S7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/arty-s7/reference-manual 21/22
The pins labeled V_P and V_N are connected to the VP_0 and VN_0 dedicated analog inputs of the FPGA. This pair of pins can also be
used as a differential analog input with voltage between 0-1V, but they cannot be used as Digital I/O. The capacitor in the circuit shown in
Figure 9.2.2 for this pair of pins is loaded on the Arty S7.
(https://reference.digilentinc.com/_media/reference/programmable-logic/arty/arty_shield_analog_single.png) Figure 9.2.2. Differential Analog Inputs
The XADC core within the Spartan-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can
be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the
Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power
rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document
titled 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter. A demo that uses
the XADC core is available on the Arty S7 resource center.
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