Datasheet
7 Series FPGAs Data Sheet: Overview
DS180 (v2.5) August 1, 2017 www.xilinx.com
Product Specification 11
I/O Electrical Characteristics
Single-ended outputs use a conventional CMOS push/pull output structure driving High towards V
CCO
or Low towards
ground, and can be put into a high-Z state. The system designer can specify the slew rate and the output strength. The input
is always active but is usually ignored while the output is active. Each pin can optionally have a weak pull-up or a weak pull-
down resistor.
Most signal pin pairs can be configured as differential input pairs or output pairs. Differential input pin pairs can optionally be
terminated with a 100Ω internal resistor. All 7 series devices support differential standards beyond LVDS: RSDS, BLVDS,
differential SSTL, and differential HSTL.
Each of the I/Os supports memory I/O standards, such as single-ended and differential HSTL as well as single-ended SSTL
and differential SSTL. The SSTL I/O standard can support data rates of up to 1,866 Mb/s for DDR3 interfacing applications.
3-State Digitally Controlled Impedance and Low Power I/O Features
The 3-state Digitally Controlled Impedance (T_DCI) can control the output drive impedance (series termination) or can
provide parallel termination of an input signal to V
CCO
or split (Thevenin) termination to V
CCO
/2. This allows users to
eliminate off-chip termination for signals using T_DCI. In addition to board space savings, the termination automatically
turns off when in output mode or when 3-stated, saving considerable power compared to off-chip termination. The I/Os also
have low power modes for IBUF and IDELAY to provide further power savings, especially when used to implement memory
interfaces.
I/O Logic
Input and Output Delay
All inputs and outputs can be configured as either combinatorial or registered. Double data rate (DDR) is supported by all
inputs and outputs. Any input and some outputs can be individually delayed by up to 32 increments of 78 ps, 52 ps, or 39 ps
each. Such delays are implemented as IDELAY and ODELAY. The number of delay steps can be set by configuration and
can also be incremented or decremented while in use.
ISERDES and OSERDES
Many applications combine high-speed, bit-serial I/O with slower parallel operation inside the device. This requires a
serializer and deserializer (SerDes) inside the I/O structure. Each I/O pin possesses an 8-bit IOSERDES (ISERDES and
OSERDES) capable of performing serial-to-parallel or parallel-to-serial conversions with programmable widths of 2, 3, 4, 5,
6, 7, or 8 bits. By cascading two IOSERDES from two adjacent pins (default from differential I/O), wider width conversions
of 10 and 14 bits can also be supported. The ISERDES has a special oversampling mode capable of asynchronous data
recovery for applications like a 1.25 Gb/s LVDS I/O-based SGMII interface.
Low-Power Gigabit Transceivers
Some highlights of the Low-Power Gigabit Transceivers include:
• High-performance transceivers capable of up to 6.6 Gb/s (GTP), 12.5 Gb/s (GTX), 13.1 Gb/s (GTH), or 28.05 Gb/s
(GTZ) line rates depending on the family, enabling the first single device for 400G implementations.
• Low-power mode optimized for chip-to-chip interfaces.
• Advanced Transmit pre and post emphasis, receiver linear equalization (CTLE), and decision feedback equalization
(DFE) for long reach or backplane applications. Auto-adaption at receiver equalization and on-chip Eye Scan for easy
serial link tuning.
Ultra-fast serial data transmission to optical modules, between ICs on the same PCB, over the backplane, or over longer
distances is becoming increasingly popular and important to enable customer line cards to scale to 100 Gb/s and onwards
to 400 Gb/s. It requires specialized dedicated on-chip circuitry and differential I/O capable of coping with the signal integrity
issues at these high data rates.
The transceiver count in the 7 series FPGAs ranges from up to 16 transceiver circuits in the Artix-7 family, up to 32
transceiver circuits in the Kintex-7 family, and up to 96 transceiver circuits in the Virtex-7 family. Each serial transceiver is a
combined transmitter and receiver. The various 7 series serial transceivers use either a combination of ring oscillators and