Datasheet

7 Series FPGAs Data Sheet: Overview
DS180 (v2.5) August 1, 2017 www.xilinx.com
Product Specification 12
LC tank or, in the case of the GTZ, a single LC tank architecture to allow the ideal blend of flexibility and performance while
enabling IP portability across the family members. The different 7 series family members offer different top-end data rates.
The GTP operates up to 6.6 Gb/s, the GTX operates up to 12.5 Gb/s, the GTH operates up to 13.1 Gb/s, and the GTZ
operates up to 28.05 Gb/s. Lower data rates can be achieved using FPGA logic-based oversampling. The serial transmitter
and receiver are independent circuits that use an advanced PLL architecture to multiply the reference frequency input by
certain programmable numbers up to 100 to become the bit-serial data clock. Each transceiver has a large number of user-
definable features and parameters. All of these can be defined during device configuration, and many can also be modified
during operation.
Transmitter
The transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 16, 20, 32, 40, 64, or 80. Additionally,
the GTZ transmitter supports up to 160 bit data widths. This allows the designer to trade-off datapath width for timing margin
in high-performance designs. These transmitter outputs drive the PC board with a single-channel differential output signal.
TXOUTCLK is the appropriately divided serial data clock and can be used directly to register the parallel data coming from
the internal logic. The incoming parallel data is fed through an optional FIFO and has additional hardware support for the
8B/10B, 64B/66B, or 64B/67B encoding schemes to provide a sufficient number of transitions. The bit-serial output signal
drives two package pins with differential signals. This output signal pair has programmable signal swing as well as
programmable pre- and post-emphasis to compensate for PC board losses and other interconnect characteristics. For
shorter channels, the swing can be reduced to reduce power consumption.
Receiver
The receiver is fundamentally a serial-to-parallel converter, changing the incoming bit-serial differential signal into a parallel
stream of words, each 16, 20, 32, 40, 64, or 80 bits. Additionally, the GTZ receiver supports up to 160 bit data widths. This
allows the FPGA designer to trade-off internal datapath width versus logic timing margin. The receiver takes the incoming
differential data stream, feeds it through programmable linear and decision feedback equalizers (to compensate for PC
board and other interconnect characteristics), and uses the reference clock input to initiate clock recognition. There is no
need for a separate clock line. The data pattern uses non-return-to-zero (NRZ) encoding and optionally guarantees
sufficient data transitions by using the selected encoding scheme. Parallel data is then transferred into the FPGA logic using
the RXUSRCLK clock. For short channels, the transceivers offers a special low power mode (LPM) to reduce power
consumption by approximately 30%.
Out-of-Band Signaling
The transceivers provide out-of-band (OOB) signaling, often used to send low-speed signals from the transmitter to the
receiver while high-speed serial data transmission is not active. This is typically done when the link is in a powered-down
state or has not yet been initialized. This benefits PCI Express and SATA/SAS applications.
Integrated Interface Blocks for PCI Express Designs
Highlights of the integrated blocks for PCI Express include:
• Compliant to the PCI Express Base Specification 2.1 or 3.0 (depending of family) with Endpoint and Root Port
capability
• Supports Gen1 (2.5 Gb/s), Gen2 (5 Gb/s), and Gen3 (8 Gb/s) depending on device family
• Advanced configuration options, Advanced Error Reporting (AER), and End-to-End CRC (ECRC) Advanced Error
Reporting and ECRC features
• Multiple-function and single root I/O virtualization (SR-IOV) support enabled through soft-logic wrappers or embedded
in the integrated block depending on family
All Artix-7, Kintex-7, and Virtex-7 devices include at least one integrated block for PCI Express technology that can be
configured as an Endpoint or Root Port, compliant to the PCI Express Base Specification Revision 2.1 or 3.0. The Root Port
can be used to build the basis for a compatible Root Complex, to allow custom FPGA-to-FPGA communication via the PCI
Express protocol, and to attach ASSP Endpoint devices, such as Ethernet Controllers or Fibre Channel HBAs, to the FPGA.
This block is highly configurable to system design requirements and can operate 1, 2, 4, or 8 lanes at the 2.5 Gb/s, 5.0 Gb/s,
and 8.0 Gb/s data rates. For high-performance applications, advanced buffering techniques of the block offer a flexible