Datasheet
7 Series FPGAs Data Sheet: Overview
DS180 (v2.5) August 1, 2017 www.xilinx.com
Product Specification 17
Revision History
The following table shows the revision history for this document:
Date Version Description of Revisions
06/21/10 1.0 Initial Xilinx release.
07/30/10 1.1 Added
SHA-256 to authentication information. Updated Table 5, Table 7, Virtex-7 FPGA Device-
Package Combinations and Maximum I/Os table (Virtex-7 T devices), and Table 9 with ball pitch
information and voltage bank information. Updated DSP and Logic Slice information in Table 8.
Updated Low-Power Gigabit Transceivers.
09/24/10 1.2 In General Description, updated 4.7 TMACS DSP to 5.0 TMACS DSP. In
Table 1, added Note 1;
updated Peak DSP Performance for Kintex-7 and Virtex-7 families. In
Table 4, updated CMT
information for XC7A175T and XC7A355T. In
Table 6, replaced XC7K120T with XC7K160T and
replaced XC7K230T with XC7K325T—and updated corresponding information. Also added
XC7K355T, XC7K420T, and XC7K480T. In Table 7,replaced XC7K230T with XC7K325T. In Table 8,
updated
XC7V450T Logic Cell, CLB, block RAM, and PCI information; updated XC7VX415T and
XC7VX690T PCI information; updated XC7V1500T, and XC7V2000T block RAM information; and
replaced XC7VX605T with XC7VX575T, replaced XC7VX895T with XC7VX850T, and replaced
XC7VX910T with XC7VX865T—and updated corresponding information. Updated
Digital Signal
Processing — DSP Slice
with operating speed of 640 MHz. Removed specific transceiver type from
Out-of-Band Signaling. In Virtex-7 FPGA Device-Package Combinations and Maximum I/Os table
(Virtex-7 T devices), replaced XC7VX605T with XC7VX575T and added table notes 2 and 3. In
Table 9, removed the FFG784 package for the XC7VX485T device; replaced XC7VX605T with
XC7VX575T; replaced XC7VX895T with XC7VX850T; and replaced XC7VX910T with XC7VX865T.
10/20/10 1.3 In Table 7, replaced XC7K120T with XC7K160T. Updated Digital Signal Processing — DSP Slice.
11/17/10 1.4 Updated maximum I/O bandwidth to 3.1 Tb/s in General Description. Updated Peak Transceiver Speed
for Virtex-7 FPGAs in Summary of 7 Series FPGA Features and in Table 1. Updated Peak DSP
Performance values in Table 1 and Digital Signal Processing — DSP Slice. In Table 7, updated
XC7K70T I/O information. In Table 8, added XC7VH290T, XC7VH580T, and XC7VH870T devices and
updated total I/O banks information for the XC7V585T, XC7V855T, XC7V1500T, and XC7VX865T
devices. In Table 9, updated XC7VX415T, XC7VX485T, XC7VX690T, XC7VX850T, and XC7VX865T
device information. Added Table 11. Updated Low-Power Gigabit Transceivers information, including
the addition of the GTZ transceivers.
02/22/11 1.5 Updated Summary of 7 Series FPGA Features and the Low-Power Gigabit Transceivers highlights and
section. In Table 1, updated Kintex-7 FPGA, Artix-7 FPGA information. In Table 4, updated XC7A175T.
Also, updated XC7A355T.
Added three Artix-7 FPGA packages to Table 5: SBG325, SBG484, and
FBG485, changed package from FGG784 to FBG784, and updated package information for
XC7A175T and XC7A355T devices. In Table 6, updated XC7K160T and added three devices:
XC7K355T, XC7K420T, and XC7K480T. In Table 7, updated XC7K70T package information and added
three devices: XC7K355T, XC7K420T, and XC7K480T. In Table 8, added note 1 (EasyPath FPGAs)
and updated note 7 to include GTZ transceivers. In Virtex-7 FPGA Device-Package Combinations and
Maximum I/Os table (Virtex-7 T devices), added two Virtex-7 FPGA packages: FHG1157 and
FHG1761, and updated XC7V1500T (no FFG1157) and XC7V2000T (no FFG1761) package
information and removed the associated notes. Added CLBs, Slices, and LUTs. Updated Input/Output.
Added EasyPath-7 FPGAs.
03/28/11 1.6 Updated General Description, Summary of 7 Series FPGA Features, Table 1, Table 4, Table 5, Table 6,
Table 7, Table 8, Table 9 (combined Virtex-7 T and XT devices in one table), and Table 11. Updated the
Low-Power Gigabit Transceivers highlights and section. Updated Block RAM, Integrated Interface
Blocks for PCI Express Designs, Configuration, Encryption, Readback, and Partial Reconfiguration,
XADC (Analog-to-Digital Converter), 7 Series FPGA Ordering Information, and EasyPath-7 FPGAs.
07/06/11 1.7 Updated General Description, Summary of 7 Series FPGA Features, Table 1, Table 4, Table 6, Table 8,
Table 9 and Table 11. Added Table 10. Added Stacked Silicon Interconnect (SSI) Technology. Updated
Transmitter, Configuration, and XADC (Analog-to-Digital Converter). Updated Figure 1.
09/13/11 1.8 Updated General Description, Table 1, Table 4, Table 5
, Table 8, CLBs, Slices, and LUTs,
Configuration, and 7 Series FPGA Ordering Information.
01/15/12 1.9 Updated General Description, Table 1, Table 4, Table 5, Table 6, Table 7, Table 8, Table 10, Table 11,
Block RAM, Digital Signal Processing — DSP Slice, Low-Power Gigabit Transceivers, Integrated
Interface Blocks for PCI Express Designs, Configuration, EasyPath-7 FPGAs, and 7 Series FPGA
Ordering Information.