Datasheet

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.2) June 20, 2017 www.xilinx.com
Preliminary Product Specification 8
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages. Values for I
OL
and I
OH
are guaranteed over the
recommended operating conditions at the V
OL
and V
OH
test points. Only selected standards are tested.
These are chosen to ensure that all standards meet their specifications. The selected standards are tested
at a minimum V
CCO
with the respective V
OL
and V
OH
voltage levels shown. Other standards are sample
tested.
Table 8: SelectIO DC Input and Output Levels
(1)(2)(3)
I/O Standard
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
V, Min V, Max V, Min V, Max V, Max V, Min mA, Max mA, Min
HSTL_I
–0.300 V
REF
–0.100 V
REF
+ 0.100 V
CCO
+ 0.300 0.400 V
CCO
– 0.400 8.00 –8.00
HSTL_I_18
–0.300 V
REF
–0.100 V
REF
+ 0.100 V
CCO
+ 0.300 0.400 V
CCO
– 0.400 8.00 –8.00
HSTL_II
–0.300 V
REF
–0.100 V
REF
+ 0.100 V
CCO
+ 0.300 0.400 V
CCO
– 0.400 16.00 –16.00
HSTL_II_18
–0.300 V
REF
–0.100 V
REF
+ 0.100 V
CCO
+ 0.300 0.400 V
CCO
– 0.400 16.00 –16.00
HSUL_12
–0.300 V
REF
–0.130 V
REF
+ 0.130 V
CCO
+ 0.300 20% V
CCO
80% V
CCO
0.10 –0.10
LVCMOS12
–0.300 35% V
CCO
65% V
CCO
V
CCO
+ 0.300 0.400 V
CCO
–0.400
Note 4 Note 4
LVCMOS15
–0.300 35% V
CCO
65% V
CCO
V
CCO
+ 0.300 25% V
CCO
75% V
CCO
Note 5 Note 5
LVCMOS18
–0.300 35% V
CCO
65% V
CCO
V
CCO
+ 0.300 0.450 V
CCO
–0.450
Note 6 Note 6
LVCMOS25
–0.300 0.7 1.700 V
CCO
+ 0.300 0.400 V
CCO
–0.400
Note 5 Note 5
LVCMOS33
–0.300 0.8 2.000 3.450 0.400 V
CCO
–0.400
Note 5 Note 5
LVTTL
–0.300 0.8 2.000 3.450 0.400 2.400
Note 6 Note 6
MOBILE_DDR
–0.300 20% V
CCO
80% V
CCO
V
CCO
+ 0.300 10% V
CCO
90% V
CCO
0.10 –0.10
PCI33_3
–0.400 30% V
CCO
50% V
CCO
V
CCO
+ 0.500 10% V
CCO
90% V
CCO
1.50 –0.50
SSTL135
–0.300 V
REF
–0.090 V
REF
+ 0.090 V
CCO
+ 0.300 V
CCO
/2–0.150V
CCO
/2 + 0.150 13.00 –13.00
SSTL135_R
–0.300 V
REF
–0.090 V
REF
+ 0.090 V
CCO
+ 0.300 V
CCO
/2–0.150V
CCO
/2 + 0.150 8.90 –8.90
SSTL15
–0.300 V
REF
–0.100 V
REF
+ 0.100 V
CCO
+ 0.300 V
CCO
/2–0.175V
CCO
/2 + 0.175 13.00 –13.00
SSTL15_R
–0.300 V
REF
–0.100 V
REF
+ 0.100 V
CCO
+ 0.300 V
CCO
/2–0.175V
CCO
/2 + 0.175 8.90 –8.90
SSTL18_I
–0.300 V
REF
–0.125 V
REF
+ 0.125 V
CCO
+ 0.300 V
CCO
/2–0.470V
CCO
/2 + 0.470 8.00 –8.00
SSTL18_II
–0.300 V
REF
–0.125 V
REF
+ 0.125 V
CCO
+ 0.300 V
CCO
/2–0.600V
CCO
/2 + 0.600 13.40 –13.40
Notes:
1. Tested according to relevant specifications.
2. 3.3V and 2.5V standards are only supported in HR I/O banks.
3. For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 2].
4. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.
5. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.
6. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks.