Datasheet

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.2) June 20, 2017 www.xilinx.com
Preliminary Product Specification 34
T
DSPDO_PCIN_CARRYCASCOUT
PCIN input to CARRYCASCOUT output. 1.56 1.85 1.85 ns
Clock to Outs from Output Register Clock to Output Pins
T
DSPCKO_P_PREG
CLK PREG to P output. 0.37 0.44 0.44 ns
T
DSPCKO_CARRYCASCOUT_PREG
CLK PREG to CARRYCASCOUT output. 0.59 0.69 0.69 ns
Clock to Outs from Pipeline Register Clock to Output Pins
T
DSPCKO_P_MREG
CLK MREG to P output. 1.93 2.31 2.31 ns
T
DSPCKO_CARRYCASCOUT_MREG
CLK MREG to CARRYCASCOUT output. 2.21 2.64 2.64 ns
T
DSPCKO_P_ADREG_MULT
CLK ADREG to P output using multiplier. 3.10 3.69 3.69 ns
T
DSPCKO_CARRYCASCOUT_ADREG_MULT
CLK ADREG to CARRYCASCOUT output using
multiplier.
3.38 4.02 4.02 ns
Clock to Outs from Input Register Clock to Output Pins
T
DSPCKO_P_AREG_MULT
CLK AREG to P output using multiplier. 4.51 5.37 5.37 ns
T
DSPCKO_P_BREG
CLK BREG to P output not using multiplier. 1.87 2.22 2.22 ns
T
DSPCKO_P_CREG
CLK CREG to P output not using multiplier. 1.93 2.30 2.30 ns
T
DSPCKO_P_DREG_MULT
CLK DREG to P output using multiplier. 4.48 5.32 5.32 ns
Clock to Outs from Input Register Clock to Cascading Output Pins
T
DSPCKO_{ACOUT; BCOUT}_
{AREG; BREG}
CLK (ACOUT, BCOUT) to {A,B} register
output.
0.73 0.87 0.87 ns
T
DSPCKO_CARRYCASCOUT_
{AREG, BREG}_MULT
CLK (AREG, BREG) to CARRYCASCOUT
output using multiplier.
4.79 5.70 5.70 ns
T
DSPCKO_CARRYCASCOUT_ BREG
CLK BREG to CARRYCASCOUT output not
using multiplier.
2.15 2.55 2.55 ns
T
DSPCKO_CARRYCASCOUT_ DREG_MULT
CLK DREG to CARRYCASCOUT output using
multiplier.
4.76 5.65 5.65 ns
T
DSPCKO_CARRYCASCOUT_ CREG
CLK CREG to CARRYCASCOUT output. 2.21 2.63 2.63 ns
Maximum Frequency
F
MAX
With all registers used. 550.66 464.25 464.25 MHz
F
MAX_PATDET
With pattern detector. 465.77 392.93 392.93 MHz
F
MAX_MULT_NOMREG
Two register multiply without MREG. 305.62 257.47 257.47 MHz
F
MAX_MULT_NOMREG_PATDET
Two register multiply without MREG with
pattern detect.
277.62 233.92 233.92 MHz
F
MAX_PREADD_MULT_NOADREG
Without ADREG. 346.26 290.44 290.44 MHz
F
MAX_PREADD_MULT_NOADREG_PATDET
Without ADREG with pattern detect. 346.26 290.44 290.44 MHz
F
MAX_NOPIPELINEREG
Without pipeline registers (MREG, ADREG). 227.01 190.69 190.69 MHz
F
MAX_NOPIPELINEREG_PATDET
Without pipeline registers (MREG, ADREG)
with pattern detect.
211.15 177.43 177.43 MHz
Table 31: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description
V
CCINT
Operating
Voltage and Speed
Grade
Units
1.0V 0.95V
-2 -1 -1L