Datasheet

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.2) June 20, 2017 www.xilinx.com
Preliminary Product Specification 47
Configuration Switching Characteristics
Table 51: Configuration Switching Characteristics
Symbol Description
V
CCINT
Operating Voltage and Speed
Grade
Units
1.0V 0.95V
-2 -1 -1L
Power-up Timing Characteristics
T
PL
(1)
Program latency. 5.00 5.00 5.00 ms, Max
T
POR
(2)
Power-on reset
(50 ms ramp rate time).
10/50 10/50 10/50
ms,
Min/Max
Power-on reset
(1 ms ramp rate time).
10/35 10/35 10/35
ms,
Min/Max
T
PROGRAM
Program pulse width. 250.00 250.00 250.00 ns, Min
CCLK Output (Master Mode)
T
ICCK
Master CCLK output delay. 150.00 150.00 150.00 ns, Min
T
MCCKL
Master CCLK clock Low time duty cycle. 40/60 40/60 40/60 %, Min/Max
T
MCCKH
Master CCLK clock High time duty cycle. 40/60 40/60 40/60 %, Min/Max
F
MCCK
Master CCLK frequency. 100.00 100.00 100.00 MHz, Max
Master CCLK frequency for AES encrypted x16.
(2)
50.00 50.00 50.00 MHz, Max
F
MCCK_START
Master CCLK frequency at start of configuration. 3.00 3.00 3.00 MHz, Typ
F
MCCKTOL
Frequency tolerance, master mode with respect to
nominal CCLK.
±50 ±50 ±50 %, Max
CCLK Input (Slave Modes)
T
SCCKL
Slave CCLK clock minimum Low time. 2.50 2.50 2.50 ns, Min
T
SCCKH
Slave CCLK clock minimum High time. 2.50 2.50 2.50 ns, Min
F
SCCK
Slave CCLK frequency. 100.00 100.00 100.00 MHz, Max
EMCCLK Input (Master Mode)
T
EMCCKL
External master CCLK Low time. 2.50 2.50 2.50 ns, Min
T
EMCCKH
External master CCLK High time. 2.50 2.50 2.50 ns, Min
F
EMCCK
External master CCLK frequency. 100.00 100.00 100.00 MHz, Max
Internal Configuration Access Port
F
ICAPCK
Internal configuration access port (ICAPE2) clock
frequency.
100.00 100.00 100.00 MHz, Max
Master/Slave Serial Mode Programming Switching
T
DCCK
/
T
CCKD
D
IN
setup/hold. 4.00/0.00 4.00/0.00 4.00/0.00 ns, Min
T
CCO
D
OUT
clock to out. 8.00 8.00 8.00 ns, Max
SelectMAP Mode Programming Switching
T
SMDCCK
/
T
SMCCKD
D[31:00] setup/hold. 4.00/0.00 4.00/0.00 4.00/0.00 ns, Min