User manual

22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/cora-z7/reference-manual 10/20
Stage 0
After the Cora Z7 is powered on, or the Zynq is reset (in software or by pressing SRST), the processor (CPU0 for the Cora Z7-10)
begins executing an internal piece of read-only code called the BootROM. If and only if the Zynq was just powered on, the BootROM
will first latch the state of the mode pins into the mode register (the mode pins are attached to JP2 on the Cora Z7). If the BootROM is
being executed due to a reset event, then the mode pins are not latched, and the previous state of the mode register is used. This means
that the Cora Z7 needs a power cycle to register any change in the programming mode jumper (JP2). Next, the BootROM copies an
FSBL from the form of non-volatile memory specified by the mode register to the 256 KB of internal RAM () within the APU (called
On-Chip Memory, or OCM). The FSBL must be wrapped up in a Zynq Boot Image in order for the BootROM to properly copy it. The
last thing the BootROM does is hand off execution to the FSBL in OCM.
Stage 1
During this stage, the FSBL first finishes configuring the PS components, such as the DDR memory controller. Then, if a bitstream is
present in the Zynq Boot Image, it is read and used to configure the PL. Finally, the user application is loaded into memory from the
Zynq Boot Image, and execution is handed off to it.
Stage 2
The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple
“Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of
the boot process, refer to Chapter 6 of the Zynq Technical Reference manual
(http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf).
The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this
image please refer to the available Xilinx documentation for these tools.
The Cora Z7 supports two different boot modes: microSD and JTAG. The boot mode is selected using the Mode jumper (JP2), which
affects the state of the Zynq configuration pins after power-on. Figure 3.1 depicts how the Zynq configuration pins are connected on the
Cora Z7.
(https://reference.digilentinc.com/_detail/reference/programmable-logic/cora-z7/cora-config.png?id=reference%3Aprogrammable-logic%3Acora-
z7%3Areference-manual)
Figure 3.1. Cora Z7 configuration pins.
The two boot modes are described in the following sections.
The Cora Z7 supports booting from a microSD card inserted into connector J10. The following procedure will allow the Zynq to boot
from microSD with a standard Zynq Boot Image created with the Xilinx tools:
1. Format the microSD card with a FAT32 file system.
2. Copy the Zynq Boot Image created with Xilinx SDK to the microSD card.
3. Rename the Zynq Boot Image on the microSD card to BOOT.bin.
4. Eject the microSD card from the host computer and insert it into connector J10 on the Cora Z7.
5. Attach a power source to the Cora Z7 and select it using JP3.
6. Place a jumper on JP2, shorting the two pins together.
7. Turn the board on. The board will now boot the image on the microSD card.
When placed in JTAG boot mode, the processor will wait until software is loaded by a host computer using the Xilinx tools. After
software has been loaded, it is possible to either let the software begin executing, or step through it line by line using Xilinx SDK.
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3.1 microSD Boot Mode
3.2 JTAG Boot Mode