User manual

22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/cora-z7/reference-manual 9/20
28 DATA4
29 DIR
30 STP
31 NXT
32 DATA0
33 DATA1
34 DATA2
35 DATA3
36 CLK
37 DATA5
38 DATA6
39 DATA7
40 CCLK
41 CMD
42 D0
43 D1
44 D2
45 D3
46 RESETN
47 CD
48 (N/C)
49 (N/C)
50 (N/C)
51 (N/C)
52 MDC
53 MDIO
Table 2.1. MIO Pinout
Unlike Xilinx FPGA devices, APSoC devices such as the Zynq-7007S are designed around the processor, which acts as a master to the
programmable logic fabric and all other on-chip peripherals in the processing system. This causes the Zynq boot process to be more
similar to that of a microcontroller than an FPGA. This process involves the processor loading and executing a Zynq Boot Image, which
includes a First Stage Bootloader (FSBL), a bitstream for configuring the programmable logic (optional), and a user application. The boot
process is broken into three stages:
3 Zynq Configuration