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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc]

https://reference.digilentinc.com/reference/programmable-logic/cora-z7/reference-manual 1/20

The Digilent Cora Z7 is a ready-to-use, low-cost, and easily embeddable development platform designed around the powerful Zynq-7000

All-Programmable System-on-Chip (APSoC) from Xilinx. The Zynq-7000 architecture tightly integrates a single or dual core 667MHz

ARM Cortex-A9 processor with a Xilinx 7-series FPGA. This pairing grants the ability to surround the processor with a unique set of

software defined peripherals and controllers, tailored for the target application.

The Cora Z7’s wide array of hardware interfaces, from a 1Gbps Ethernet PHY to analog-to-digital converters and general-purpose

input/output pins, make it an ideal platform for the development of a vast variety of embedded applications. The small form factor and

mounting holes make the Cora Z7 ready to be used as one component of a larger solution. The on-board SD Card slot, Ethernet, and

Power solution allow the Cora Z7 to operate independently of a host computer.

(https://reference.digilentinc.com/_media/reference/programmable-logic/cora-z7/cora-obl-600.png)

Cora Z7 Reference Manual

Summary of content (20 pages)

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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] Cora Z7 Reference Manual The Digilent Cora Z7 is a ready-to-use, low-cost, and easily embeddable development platform designed around the powerful Zynq-7000 All-Programmable System-on-Chip (APSoC) from Xilinx. The Zynq-7000 architecture tightly integrates a single or dual core 667MHz ARM Cortex-A9 processor with a Xilinx 7-series FPGA.
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2.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] https://reference.digilentinc.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] Features ZYNQ Processor 667MHz dual-core (*single-core) Cortex-A9 processor FPGA Programmable logic equivalent to Artix-7 FPGA 4,400 Programmable logic slices (*3,600) 80 DSP slices (*60) 270 KB of block RAM () (*225 KB) DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports High-bandwidth peripheral controllers: 1G Ethernet, USB 2.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] Gigabit Ethernet PHY with 48-bit globally unique EUI-48/64™ compatible identifier available on sticker USB-JTAG programming circuitry USB-UART bridge USB OTG PHY (supports host only) Push-buttons and LEDs Two Push-buttons Two RGB LEDs Expansion Connectors Two Pmod connectors 16 Total FPGA I/O Arduino/chipKIT Shield connector Up to 49 Total FPGA Digital I/O 6 Single-ended 0-3.3V Analog inputs to XADC 8 Differential 0-1.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] Callout Description Callout Description 9 User tri-color LEDs 19 DDR3L memory 10 User push buttons Purchasing Options and Board Variants The Cora Z7 can be purchased with either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] Functional Description 1 Power Supplies The Cora Z7 requires a 5 Volt power source to operate. This power source can come from the Digilent USB-JTAG port (J12) or it can be derived from a 5 Volt DC power supply connected to the Power Jack (J15). Unlike other Digilent FPGAs, the Cora Z7 cannot be powered through the Shield Header. A red power-good LED () (LD7), driven by the 3.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] Table 1.1. Cora Z7 Power Rails. 1) With JP3 set to “USB” 2 Zynq APSoC Architecture The Zynq APSoC is divided into two distinct subsystems: The Processing System (PS) and the Programmable Logic (PL). Figure 2.1 shows an overview of the Zynq APSoC architecture, with the PS colored light green and the PL in yellow. Note that the PCIe Gen2 controller and Multi-gigabit transceivers are not available on the Zynq-7010 or Zynq-7007S devices.
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22.8.2018 Pin Cora Z7 Reference Manual [Reference.Digilentinc] Configuration Mode ENET 0 USB 0 Shield UART 0 0 (N/C) 1 (N/C) 2 MODE0 3 MODE1 4 MODE2 5 MODE3 6 MODE4 7 VCFG0 8 VCFG1 9 Ethernet Reset 10 Ethernet Interrupt 11 USB Over Current 12 Shield Reset 13 (N/C) 14 UART Input 15 UART Output MIO 501 (1.0V) Peripherals Pin ETH 0 16 TXCK 17 TXD0 18 TXD1 19 TXD2 20 TXD3 21 TXCTL 22 RXCK 23 RXD0 24 RXD1 25 RXD2 26 RXD3 27 RXCTL https://reference.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] 28 DATA4 29 DIR 30 STP 31 NXT 32 DATA0 33 DATA1 34 DATA2 35 DATA3 36 CLK 37 DATA5 38 DATA6 39 DATA7 40 CCLK 41 CMD 42 D0 43 D1 44 D2 45 D3 46 RESETN 47 CD 48 (N/C) 49 (N/C) 50 (N/C) 51 (N/C) 52 MDC 53 MDIO Table 2.1.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] Stage 0 After the Cora Z7 is powered on, or the Zynq is reset (in software or by pressing SRST), the processor (CPU0 for the Cora Z7-10) begins executing an internal piece of read-only code called the BootROM. If and only if the Zynq was just powered on, the BootROM will first latch the state of the mode pins into the mode register (the mode pins are attached to JP2 on the Cora Z7).
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] It is also possible to directly configure the PL over JTAG, independent of the processor. This can be done using the Vivado Hardware Server. 4 DDR3L Memory The Cora Z7 includes a Micron MT41K256M16HA-125 DDR3L memory component, creating a single rank 16-bit wide interface and a total of 512 MiB (Mebi-byte, or 536,870,912 bytes) of capacity.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] modes, but does not support SPI mode. Based on the  Zynq Technical Reference manual (http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf), SDIO host mode is the only mode supported.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] 8 Ethernet PHY The Cora Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 APSoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to MIO pins MIO10 and MIO9, respectively. (https://reference.digilentinc.com/_media/reference/programmable-logic/cora-z7/cora-ethernet.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] For more information on using the Gigabit Ethernet MAC, refer to the  Zynq Technical Reference manual (http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf). 9 Clock Sources The Cora Z7 provides a 50 MHz () clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System (PS) subsystems.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] 11 Basic I/O The Cora Z7 board includes two tri-color LEDs and 2 push buttons as shown in Figure 11.1. The push buttons are connected to the Zynq PL via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button was inadvertently defined as an output).
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] The High-speed Pmods have their data signals routed as impedance matched differential pairs for maximum switching speeds. They have pads for loading resistors for added protection, but the Cora Z7 ships with these loaded as 0-Ohm shunts. With the series resistors shunted, these Pmods offer no protection against short circuits, but allow for much faster switching speeds.
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22.8.2018 Cora Z7 Reference Manual [Reference.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] The pins labeled A0-A11 and V_P/V_N are used as analog inputs to the XADC module of the FPGA. The FPGA expects that the inputs range from 0-1 V. On the pins labeled A0-A5, the Cora Z7 uses an external circuit to scale down the input voltage from 3.3V. This circuit is shown in Figure 13.2.1. This circuit allows the XADC module to accurately measure any voltage between 0V and 3.
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22.8.2018 Cora Z7 Reference Manual [Reference.Digilentinc] 14 Unloaded Expansion Header The Cora Z7 has an additional 12 Digital I/O pins in the form of a 16-pin unloaded expansion header (J1). The two outer-most pins (labeled V) of this header are connected to the Cora Z7's 3.3V rail. The next two outermost pins (labeled G) are connected to ground. The remaining 12 pins (labeled IO2-IO13) are directly connected to the Zynq PL.
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