User manual

22.8.2018 Pmod I2S2 Reference Manual [Reference.Digilentinc]

https://reference.digilentinc.com/reference/pmod/pmodi2s2/reference-manual 5/9

The Pmod I2S2 utilizes a (Cirrus Logic CS4344 Stereo D/A () converter) to take digital audio data and output the corresponding analog

signal through a standard stereo headphone jack (labeled Line Out). In addition, a (Cirrus Logic CS5343 Stereo A/D () converter) is used

to convert analog audio signals from a second 3.5mm audio jack (labeled Line In) into digital audio data. It is designed to work at a wide

variety of standard audio sampling rates.

The two primary integrated circuits of the Pmod I2S2 communicate with the host board via the (GPIO () protocol). As each IC uses the

Integrated Interchip Sound (I2S) protocol, several different clock lines are required, as described (below).

The CS4344 and CS5343 (henceforth referred to as the “line-out converter” and “line-in converter”, respectively) are each connected (to

the host board) via their own I2S interface. As seen in the (Pinout table) above, the line-out converter's I2S interface is connected to the

top row interface of Pmod connector J1, while the line-in converter's I2S interface is connected to the bottom row.

Any external power applied to the Pmod I2S must be within 3 V and 5.25 V; however, it is recommended that Pmod is operated at 3.3 V.

Digital logic levels must correspond to the power supply voltage.

The fastest clock signal of each I2S interface will be the Master Clock (MCLK); as the name implies, this signal will keep everything nicely

synchronized. The Left-Right Clock (LRCK), also known as the Word Select Clock, indicates whether a particular set of data is associated

with the left or right audio channel for stereo sound.

The final clock is the Serial Clock (SCLK ()), also known as the Bit Clock. The line-in and line-out converters can each either be provided

this clock signal, or generate it internally. More information on how the serial clocks for each converter can be found (below).

The I2S protocol requires that data is clocked in on the falling edge of SCLK (). The first bit of data (MSB) is not clocked in on the

falling edge until the first complete serial clock cycle has passed after LRCK has changed state. Data must be valid on the rising edge of

SCLK ().

NOTE: The term “I2S input/output sample rate” refers to the frequency that a full frame of data, consisting of both the left and right

channels, is transmitted over an I2S interface.

An example timing diagram of a single I2S frame is shown below.

The line-out converter will internally derive its SCLK () if it is provided at least two consecutive frames of the LRCK without providing

any SCLK () signals. In this case, the line-out converter will measure the MCLK and LRCK rates and determine an appropriate SCLK ()

rate. However, the MCLK/LRCK ratio must meet one of several specific ratios in order to properly generate SCLK (), as outlined in the

table below from the CS4344 datasheet.

Internal SCK Mode External SCK Mode

16-bit data and SCK = 32*Fs if MCLK/LRCK = 1024, 512, 256, 128, or

Up to 24-bit data with data valid on the rising edge of

SCK

Up to 24-bit data and SCK = 48*Fs if MCLK/LRCK = 768, 384, 192, or

Up to 24-bit data and SCK = 72*Fs if MCLK/LRCK = 1152

The ratio between the MCLK and LRCK rates must be an integer ratio so that the line-out converter's internal clock dividers can

determine an appropriate bit rate. A table of commonly used sample rates and their corresponding MCLK rates, from the CS4344

datasheet, is provided below.

LRCK (kHz ()) MCLK (MHz ())

Functional Description

Serial Communication

I2S Overview

Line Out Serial Clock Generation