User manual
22.8.2018 Pmod I2S2 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/pmod/pmodi2s2/reference-manual 6/9
64x 96x 128x 192x 256x 384x 512x 768x 1024x 1152x
32 - - - - 8.1920 12.2880 - - 32.7680 36.8640
44.1 - - - - 11.2896 16.9344 22.5792 33.8680 45.1580 -
48 - - - - 12.2880 18.4320 24.5760 36.8640 49.1520 -
64 - - 8.1920 12.2880 - - 32.7680 49.1520 - -
88.2 - - 11.2896 16.9344 22.5792 33.8680 - - - -
96 - - 12.2880 18.4320 24.5760 36.8640 - - - -
128 8.1920 12.2880 - - 32.7680 49.1520 - - - -
176.4 11.2896 16.9344 22.5792 33.8680 - - - - - -
192 12.2880 18.4320 24.5760 36.8640 - - - - - -
Mode QSM DSM SSM
The line-in converter can be placed in either Master Mode or Slave Mode by setting mode jumper JP1 to the corresponding position. The
position of this jumper should not be changed while the Pmod I2S2 is powered on.
In Slave Mode, LRCK and SCLK () must be generated by the host board. Supported sample rate ranges and their corresponding
MCLK/LRCK and SCLK ()/LRCK ratios are provided in the table below from the CS5343 datasheet. The line-in converter
automatically selects as needed from single- and double-speed modes.
Speed Mode MCLK/LRCK Ratio SCLK ()/LRCK Ratio Input Sample Rate Range (kHz ())
Single-Speed Mode 256x 64 4-24, 43-54
512x 64 43-54
384x 64 4-24, 43-54
784x 64 43-54
Double-Speed Mode 128x 64 86-108
256x 64 86-108
192x 64 86-108
384x 64 86-108
In Master Mode, both LRCK and SCLK () are automatically generated by the line-in converter. For Master Mode, the provided MCLK
rate must be within the range of 4-54 KHz. Once the line-in converter has powered up, it automatically selects an MCLK/LRCK ratio of
256x/512x, depending on the MCLK rate.
Note: The CS5343's Double-Speed Mode is not available in Master Mode on the Pmod I2S2.
A table of common MCLK frequencies, for both Master and Slave Modes, with their corresponding MCLK/LRCK ratios and audio
sample rates, from the CS5343 datasheet, is provided below.
Master and Slave Mode
Sample Rate (kHz ()) Speed Mode MCLK (MHz ()) MCLK (MHz ())
256x 512x 384x 768x
Line In Serial Clock Generation