User Manual

The Zmod
DAC () was designed to be a piece in a modular, HW and SW open-source ecosystem. Combined with a SYZYGY™ carrier,
other SYZYGY™ compatible pods, Zmod
DAC () can be used for a variety of applications: data acquisition systems, closed loop
controllers, etc.
This document describes the Zmod
DAC ()'s circuits, with the intent of providing a better understanding of its electrical functions,
operations, and a more detailed description of the hardware’s features and limitations. It is not intended to provide enough information
to enable complete duplication of the Zmod
DAC (), but can help users to design custom configurations for programmable parts in the
design.
Channels: 2
Channel type: single ended
Resolution: 14-bit
Output Range: ±1.25V (Low Range); ±5V (High Range)
Absolute Resolution: 167μV (Low Range); 665μV (High Range)
Accuracy - typical ± 0.2% of Range
Output impedance: 50Ω
Sample rate (real time): 100MS/s.
AC amplitude (max): ±5 V.
Analog bandwidth: 40 MHz () @ 3dB, 20 MHz () @ 0.5dB, 14 MHz () @ 0.1dB
Slew rate (2V step): 180V/μs
The Arbitrary Outputs/AWG instrument block includes:
DAC (): the digital-to-analog converter for both AWG channels
AWG ref: refernce voltage for the DAC ()
I/V: cur
rent to bipolar voltage converters
Out: output stages
Protection: output stages protection circuitry
The Power Supplies and Control block generates all internal supply voltages.
The MCU works as a I2C memory for two different purposes:
The DNA includes the standard SYZYGY™ (https://syzygyfpga.io) pod identification information.
The Calibration Memory stores all calibration parameters. The Zmod
DAC
() includes no analog calibration circuitry.
Instead, a calibration operation is performed at manufacturing (or by the user), and parameters are stored in memory. The
application software uses these parameters to correct the generated signals
In the sections that follow, schematics are not shown separately for identical blocks. For example, the AWG I/V schematic is only shown
for channel 1 since the schematic for channel 2 is identical. Indexes are omitted where not relevant. As examples, in equation below,
does not contain the channel index (because the equation applies to both channels 1 and 2).
Features
1. Architectural Overview and Block Diagram
Zmod ADC ()'s high-level block diagram is presented in Fig. 2 below. The core of the Zmod ADC () is the dual channel, high speed, low
power, 14-bit, 125MS/s DAC (),

AD9717 ). The carrier board is responsible to configure the internal registers of the DAC () circuit,
provide the acquisition clock and generate the data.
The Analog Output block is also called the AWG (Arbitrary Waveform Generator), because of similar structure and behavior to such a
front end. The signals in this circuitry use “AWG” indexes, to indicate they are related to the AWG block. Signal and equations also use
certain naming conventions. Analog voltages are prefixed with a “V” (for voltage), and suffixes and indexes are used in various ways: to
specify the location in the signal path (OUT, DAC (), etc.); to indicate the related instrument (AWG, etc.); and to indicate the channel (1
or 2). Referring to the block diagram in Fig. 2 below:

2
V
outAWGFS