User Manual

The USB104 A7 includes a high-retention USB-B port intended for all communication with a host computer. This port is connected to a
USB hub which breaks out the traffic into several different FPGA-connected interfaces, via a FTDI FT2232HQ USB-UART bridge and
a FTDI FT232H hi-speed single-channel USB to UART/FIFO bridge. The USB hub and the two controller are transparent to the user.
A UART interface (referred to as the USB-UART Bridge), the USB-JTAG programming interface, and a parallel data interface (DPTI)
are implemented. The USB JTAG programming functionality is discussed in the
FPGA Configuration section of this document. The
UART and DPTI interfaces are detailed below. Each of these three interfaces is presented to the host computer as its own serial port.
Note: The hub and bridge circuitry of the USB104 A7 is designed such that the interfaces do not interfere with one another. For example, programmers
interested in using the UART or parallel transfer functionality of the USB104 A7 within their design do not need to worry about the JTAG circuitry interfering
with the UART data transfers, and vice-versa.
As long as mode switch SW1/4 is placed in the “HCFG” position, the Platform MCU configures the USB hub at power-on. Placing the
switch in the “RECO” position makes the USB port and hub receive power from the host system, and is intended to be used only for
firmware recovery, when the PMCU cannot be depended on for configuration.
The DPTI interface is an 8-bit wide parallel FIFO-style data interface supporting both asynchronous and synchronous modes. In FTDI
terminology, DPTI is equivalent to “FT245-style Asynchronous or Synchronous FIFO Interface”. It is available in both synchronous and
asynchronous modes, configurable from the DPTI
API (). In synchronous mode, data transfer is timed by the clock provided by the USB
controller (connected to the FPGA on pin P17). In asynchronous mode, data transfer occurs on transitions of the read and write control
signals. THe USB controller emulates a FIFO memory, providing status signals about the availability of data to be read and free space for
data to be written. The FPGA controls data transfer through read, write, and output enable signals. Data transfer speeds of up to 40
MB
()/s are supported in synchronous mode. This interface is summarized in Figure 6.1.1, below:
Figure 6.1.1 USB104 A7 DPTI Connections
Table 6.1.1. DPTI Signal Descriptions
Signal
Direction
(FPGA) Description
D[7:0] I/O Data bus.
RXE# Input When low, data is available to be read from the FIFO.
TXE# Input When low, data can be written to the FIFO.
6. USB Port
6.1. DPTI P
arallel Data Transfer Interface