User Manual

Net
Name
Upstream
Net Name
Power
IC Type
Power
IC Label
Min/Typ/Max
Voltage
Max
Current Major Devices and Connectors
Net
Name
Upstream
Net Name
Power
IC Type
Power
IC Label
Min/Typ/Max
Voltage
Max
Current Major Devices and Connectors
VCC1V0 VCC5V0 Buck IC14 1.0V +- 5% 2.5A FPGA
VCC1V8 VCC5V0 Buck IC14 1.8V +- 5% 1.0A FPGA, USB JTAG/UART
DDRVCC VCC5V0 Buck IC14 1.35V/1.5V +-
5%
2.0A FPGA, DDR3/DDR3L
DDRVTT DDRVCC,
VCC5V0
LDO IC11 0.675V/0.75V
+- 5%
0.43A DDR3/DDR3L
VCC3V3 VCC5V0 Buck IC17 3.3V +- 5% 3.0A FPGA, Zmod, Pmods, USB Hub, USB
JTAG/UART, USB DPTI/DSPI
VADJ VCC5V0 Buck IC14 1.2V +- 5% to
3.3V +- 5%
1.2A FPGA, Zmod
SYZ5V0 VCC5V0 Load
Switch
IC16 5.0V +- 5% 1.5A Zmod
Depending on DDR voltage select switch position
The power-on sequence for the USB104 A7 is controlled by the connections between the power-good and enable pins of the supplies.
The sequence is started when a power input source is connected to the board. The power supplies shut down in the opposite order when
both input sources are disconnected. The startup sequence is as follows:
1. VCC5V0, SYZ5V0
2. VCC1V0
3. VCC1V8
4. DDRVCC/DDRVTT
5. VCC3V3
6. VADJ
1)
2)
1.3. Power Sequencing
Note: The VADJ rail may or may not be powered on, depending on the PMCU configuration and whether a Zmod or other SYZYGY pod is installed.
1.4. Platform MCU
As noted in previous sections, the USB104 A7 uses an Atmega328PB microcontroller (IC12), referred to as the Platform MCU (PMCU),
to implement the SmartVIO requirements of the SYZYGY standard, set the DDR voltage, configure the USB Hub, and provide
information about the power supply settings and SYZYGY ports to the FPGA.
The Platform MCU enumerates the SYZYGY port and determines the power needs of an installed module. The power budget of the
USB104 A7 is then determined based on the needs of the Zmod, as well as other peripherals.
The PMCU firmware for the USB104 A7 supports setting the DDR operating voltage based on the position of the DDR voltage select
switch (SW1/2). The state of this switch is only read during the power-on sequence.
If the hub configuration/recovery select switch (SW1/4) is placed in the “HCFG” position at power-up, the Platform MCU configures it
to automatically detect which power input source is used and correctly report whether the board is self or bus powered to the USB host.
Note: Switches SW1/3 and SW1/4 are intended for restoration of and updates to the Platform MCU firmware and the USB Hub configuration. Please
reach out to Digilent Support on the Programmable Logic section of the
Digilent Forum (https://forum.digilentinc.com in the event that your board needs to be
reflashed. For normal operation, SW1/3 and SW1/4 should be left in the “NORM” and “HCFG” positions, respectively.
When the USB104 A7 is turned on, the PMCU enumerates the pods attached to the USB104 A7's SYZYGY ports and retrieves their
DNA, in order to correctly configure the variable supplies.
After SYZYGY enumeration is complete, the PMCU configures itself as an I2C slave device with a chip address of 0x60. Control of the
I2C bus is then handed over to the FPGA, with SCL and SDA connected to FPGA pins U16 and V17, respectively.