User Manual

After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. The FPGA can be
configured in one of two ways:
1. A PC can use the Digilent USB-JTAG circuitry connected to the USB port (J2, labeled “USB”), to program the FPGA any time
the power is on.
2. A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA using the SPI port.
Figure 2.1: USB104 A7 Configuration Options
Figure 2.1 shows the different options available for configuring the FPGA. An on-board programming mode select switch (SW1/1)
selects between the programming modes.
The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The Vivado software from Xilinx can
create bitstreams from VHDL, Verilog®, or schematic-based source files.
Bitstreams are stored in SRAM-based memory cells within the FPGA. This data defines the FPGA’s logic functions and circuit
connections. The data remains valid until it is erased by removing board power, by pressing the reset button (BTNP, labeled “PROG”)
attached to the PROG input, or by writing a new configuration file to the FPGA using the JTAG port.
An Artix-7 100T bitstream is typically 30,606,304 bits and can take a long time to transfer. The time it takes to program the USB104 A7
can be decreased by compressing the bitstream before programming, and then allowing the FPGA to decompress the bitstream itself
during configuration. Depending on design complexity, compression ratios of 10x can be achieved. Bitstream compression can be
enabled within the Xilinx tools (Vivado) to occur during the generation of the bitstream. For instructions on how to do this, consult the
Xilinx documentation for the toolset used. After being successfully programmed, the FPGA will cause the “DONE”
LED () (LD5) to
illuminate. Pressing the “PROG” button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will
immediately attempt to reprogram itself from whatever method has been selected by the programming mode jumpers.
The following sections provide greater detail about programming the USB104 A7 using the different methods available.
Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as
JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry
(connected to port J2, labeled “USB”) or an external JTAG programmer, such as the Digilent JTAG-HS2, attached to port J3. JTAG
programming can be performed any time after the USB104 A7 has been powered on, regardless of what the programming mode select
switch (SW1/1) is set to. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being
transmitted over JTAG. Setting the mode switch to the JTAG setting (seen in Figure 2.1) can be used to prevent the FPGA from being
configured from any other bitstream source until JTAG programming occurs. The maximum recommended JTAG frequency is 30
MHz
().
Programming the USB104 A7 with an uncompressed bitstream using the onboard USB-JTAG circuitry usually takes around 5 seconds.
JTAG programming can be done using Vivado's hardware manager.
Since the FPGA on the USB104 A7 is volatile, it relies on the Quad-SPI flash memory to store the configuration between power cycles.
This configuration mode is called Master SPI. The blank FPGA takes the role of master and reads the configuration file out of the flash
device upon power-up. To that effect, a configuration file needs to first be downloaded to the flash. When programming a nonvolatile
flash device, a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a circuit that can
program flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by
the Xilinx tools). This is called indirect programming. After the flash device has been programmed, it can automatically configure the
FPGA at a subsequent power-on or reset event as determined by the mode switch setting (see Figure 3). Programming files stored in the
flash device will remain until they are overwritten, regardless of power-cycle events.
Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory
technology. Once written however, FPGA configuration can be very fast—less than a second. Bitstream compression, SPI bus width, and
configuration rate are factors controlled by the Xilinx tools that can affect configuration speed. The USB104 A7 supports x1, x2, and x4
bus widths and data rates of up to 50
MHz () for Quad-SPI programming.
Quad-SPI programming can be done using Vivado's hardware manager.
2. FPGA Configuration
2.1. JTAG Configuration
2.2. Quad SPI Configuration