User Manual

The USB104 A7 includes one MT41K256M16TW-107 memory component, creating a single rank, 16-bit wide interface with 512MB of
capacity. It is routed to an HR (High Range) FPGA bank, powered at either 1.35V or 1.5V (discussed in Section 3.1,
DDR3 Voltage
Levels, below), with 40 ohm controlled single-ended trace impedance. 40 ohm internal terminations in the FPGA are used to match the
trace characteristics. Similarly, on the memory side, on-die terminations (ODT) are used for impedance matching.
For proper operation of the memory, a memory controller and physical layer (PHY) interface needs to be included in the FPGA design.
The easiest way to accomplish this on the USB104 A7 is to use the Xilinx 7-series memory interface solutions core generated by the MIG
(Memory Interface Generator) Wizard. The MIG Wizard can generate a native FIFO-style or an AXI4 interface to connect to user logic.
This workflow allows the customization of several DDR parameters optimized for the particular application. Table 3.1 below lists the
MIG Wizard settings optimized for the USB104 A7 (any settings not mentioned can be left in default state).
Table 3.1: Memory Interface Generator Settings for the USB104 A7
Setting 1.5V 1.35V
Memory type DDR3 SDRAM DDR3 SDRAM
Max. clock period 2500ps (800 MT/s data rate) 3000ps (666.66 MT/s data rate)
Memory part MT41K256M16XX-107 MT41K256M16XX-107
Memory Voltage 1.5V 1.35V
Data width 16 16
Data mask Enabled Enabled
Recommended Input Clock Period 5000ps (200.000
MHz ()) 6000ps (166.667 MHz ())
Read Burst Type and Length Sequential Sequential
Output Driver Impedance Control RZQ/6 RZQ/6
Rtt (nominal) – On-die termination RZQ/6 RZQ/6
Controller Chip Select pin Disabled Disabled
Internal Vref Enabled Enabled
Internal termination impedance 40ohms 40ohms
For clocking, it is recommended that the System clock be set to “No buffer”, and connected to a 200MHz clock generated by a Clocking
Wizard IP using the onboard 100MHz oscillator on pin E3 as input. The Reference clock should be set to “Use system clock”.
For your convenience, both an importable UCF file and importable PRJ files for the 1.5V and 1.35V configurations have been provided
on the
USB104 A7 Resource Center (https://reference.digilentinc.com/reference/programmable-logic/usb104a7/start) to speed up the process
of configuring the MIG.
For those using the MIG with a MicroBlaze project, the USB104 A7 MIG settings and pinout can be automatically imported from
Digilent's Vivado Board Files, which can be installed into Vivado by following the steps presented in Section 3 of the
Installing Vivado,
Xilinx SDK, and Digilent Board Files (https://reference.digilentinc.com/vivado/installing-vivado/start) guide. The configuration imported
from the board files is intended for use with the clocking scheme discussed above, without additional configuration.
For more details on the Xilinx MIG, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (Xilinx UG586).
The USB104 A7 supports two voltage levels for the DDR3/DDR3L memory. The Platform MCU reads the position of the DDR
voltage select switch (SW1/2) during powerup, and sets the rail voltages appropriately. While the select switch can be set for 1.35V so
that the board uses less power, this comes with a performance tradeoff, and is intended only for advanced users. The MIG.prj file
provided with Digilent's board files for the USB104 A7 is intended for use with the 1.5V setting, and requires additional configuration for
use with the 1.35V setting.
Table 1.4.1: DDR Voltage Select Switch Settings
Switch Position DDRVCC Voltage DDRVTT Voltage
3. DDR3/DDR3L Memory
3.1. DDR3 Volta
ge Levels