User Manual

Switch Position DDRVCC Voltage DDRVTT Voltage
1.5V (OFF) 1.5V 0.75V
1.35V (ON) 1.35V 0.675V
FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number S25FL128SAGMF100), and setting the
programming mode select switch (SW1/0) will cause the FPGA to automatically read a configuration from this device at power on. An
Artix-7 100T configuration file requires 30,606,304 bits of memory, leaving about 76% of the flash device (or ~12MB) available for user
data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory (typically 128
KB). These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to
automatically generate this bootloader, roll it into a single file (called an .mcs file) that also contains the bitstream and your custom
Microblaze application, and program this file into SPI Flash using Xilinx SDK and Vivado. See Xilinx Answer Record 63605 for more
information.
The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is
outside the scope of this document. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration. On other
boards, SCK is an exception because it remains a dedicated pin even after configuration, however, on the USB104 A7 the SCK signal is
routed to an additional general purpose pin (L16) that can be accessed after configuration (see Figure 4.1 below). This allows access to
this pin without having to instantiate the special FPGA primitive called STARTUPE2.
Xilinx's AXI Quad SPI core can be used to read/write the flash in a Microblaze design. Refer to Xilinx's product guide for this core to
learn more about using it, or to Micron's datasheet for the flash device to learn how to implement a custom controller.
Figure 4.1 USB104 A7 SPI Flash
The USB104 A7 includes a 100
MHz () crystal oscillator connected to pin E3, an MRCC input on FPGA bank 35.
Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will
properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The
wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design.
The clocking wizard can be accessed from within the Vivado and IP Integrator tools.
The 100
MHz () clock is intended as both a general purpose system clock, and to drive the system clock input of the Memory Interface
Generator (MIG) IP Core to allow for proper use of the DDR3/DDR3L memory. Section 3,
DDR3/DDR3L Memory, describes how to
use this clock properly with the MIG. For complete information on using the MIG, see the 7 Series FPGAs Memory Interface Solutions
User Guide (ug586) from Xilinx.
4. Quad-SPI Flash
5.
Oscillators/Cloc
ks