Datasheet

Platform Cable USB
DS300 (v3.3) June 25, 2014 www.xilinx.com
Product Specification 10
R
TDI_DIN_MOSI and TMS_PROG_SS Timing Specifications
For JTAG, SPI, and slave-serial configuration modes, the
TDI_DIN_MOSI and TMS_PROG_SS outputs change on
falling edges of TCK_CCLK_SCK (Figure 18). Target
devices sample TDI_DIN_MOSI and TMS_PROG_SS on
rising edges of TCK_CCLK_SCK. The minimum setup time
T
TTSU(MIN)
for target device sampling of TDI_DIN_MOSI or
TMS_PROG_SS is:
T
TTSU(MIN)
=T
CLK/2
– T
CPD(MAX)
= 20.83 ns – 9.2 ns
= 11.63 ns
where T
CLK/2
is the TCK_CCLK_SCK Low time at 24 MHz,
and T
CPD(MAX)
is the maximum TDI_DIN_MOSI or
TMS_PROG_SS propagation delay relative to
TCK_CCLK_SCK inherent in the output stage of the cable.
Reducing the TCK_CCLK_SCK frequency increases the
data setup time at the target.
Note:
Timing specifications apply when VREF = 3.3V. Operation
at 24 MHz might not be possible when using a VREF below 3.3V
due to the increased propagation delay through the output buffer
stage of the cable.
TDO/MISO Timing Issues
When read operations are being performed in Boundary-Scan
or SPI mode, there must be sufficient time during each one-
half clock cycle for TDO/MISO to propagate back to the cable
for sampling. Figure 19, Figure 20, page 11, and Figure 21,
page 12 illustrate a potential problem when a 24 MHz
TCK_CCLK_SCK frequency is selected. An output buffer in
Platform Cable USB introduces a phase delay of 4 ns between
the cable and the target. (See cursors C1 and C2 in Figure 19,
page 11 for the CBL_TCK to TCK_CCLK_SCK delay.)
The target device has a variable propagation delay from the
negative edge of TCK_CCLK_SCK to assertion of
TDO_DONE_MISO. (Refer to Figure 20 for the
TCK_CCLK_SCK to TDO_DONE_MISO delay.) For
example, Figure 20 shows a 12 ns TDO delay for an
XC2C256-VQ100 CPLD.
Finally, signal conditioning circuitry in Platform Cable USB
introduces a third phase delay of approximately 12 ns between
TDO_DONE_MISO and the logic that samples the signal.
Note:
(Refer to Figure 21, page 12 for the TDO_DONE_MISO to
CBL_TDO delay.)
Data is sampled approximately 11 ns after the rising edge of
CBL_TCK. The total propagation delay must be carefully
considered to successfully operate at 24 MHz. Refer to
Figure 30, page 19 for set-up timing requirements.
X-Ref Target - Figure 18
Figure 18: TDI_DIN_MOSI and TMS_PROG_SS Timing with Respect to TCK_CCLK_SCK
DS300_17_021707
TDI_DIN_MOSI Changes
on Negative Edge of
TCK_CCLK_SCK (G2)
TMS_PROG_SS Changes on Negative
Edge of TCK_CCLK_SCK (G1)