Datasheet

Platform Cable USB
DS300 (v3.3) June 25, 2014 www.xilinx.com
Product Specification 12
R
Target Reference Voltage Sensing (V
REF
)
Platform Cable USB incorporates an over-voltage clamp on
the V
REF
pin of the 2 mm ribbon cable connector. The
clamped voltage (V
REF_A
) supplies a high-slew-rate buffer
(NC7SZ125) that drives each of the three output signals.
V
REF
must be a regulated voltage.
Note:
Do not insert a current-limiting resistor in the target system
between the VREF supply and pin 2 on the 2 mm connector.
No damage to Platform Cable USB occurs if the A-B cable
is unplugged from the host while the ribbon cable or flying
leads are attached to a powered target system. Similarly, no
damage to target systems occurs if Platform Cable USB is
powered and attached to the target system while the target
system power is off.
Buffers for the output signals (TCK_CCLK_SCK,
TMS_PROG_SS, and TDI_DIN_MOSI) are set to high-Z
when V
REF
drops below 1.40V. The output buffer amplitude
linearly tracks voltage changes on the V
REF
pin when
1.40V ≤ V
REF
≤ 3.30V. Amplitude is clamped at
approximately 3.30V when 3.30 ≤ V
REF
≤ 5.00V.
Refer to Ta ble 4 for the relationship between V
REF
voltage
and output signal amplitude.
Xilinx applications actively drive the outputs to logic 1 before
setting the respective buffer to high-Z, avoiding the
possibility of a slow rise-time transition caused by a charge
path through the pull-up resistor into parasitic capacitance
on the target system.
Output Driver Structure
Platform Cable USB drives three target signals:
TCK_CCLK_SCK, TMS_PROG_SS, and TDI_DIN_MOSI.
Each of these signals incorporates the same driver
topology. A Xilinx XC2C256 Coolrunner-II CPLD generates
the output signals.
Each signal is routed to an external NC7SZ125 high-speed
CMOS buffer (Figure 22). Series-damping resistors (30Ω)
reduce reflections. Weak pull-up resistors (20 kΩ) maintain
a defined logic level when the buffers are set to high-Z. The
pull-up resistors terminate to V
REF_A
.
X-Ref Target - Figure 21
Figure 21: TDO_DONE_MISO Timing with Respect to TCK_CCLK_SCK (TDO_DONE_MISO to CBL_TDO Delay)
DS300_20_110204
Tabl e 4: Output Signal Level as a Function of the V
REF
V
REF
Voltage on Target
System (VDC)
Output Signal
Levels (VDC)
Status LED
Color
0.00 ≤ V
REF
< 1.40 High-Z Amber
1.40 ≤ V
REF
< 3.30 V
REF
Green
3.30 ≤ V
REF
≤ 5.00 ≅ 3.3 Green
Notes:
1. There are weak pull-up resistors to VREF_A on each of the three
output drivers (TCK_CCLK_SCK, TMS_PROG_SS, and
TDI_DIN_MOSI). The output drivers are active only during
configuration and programming operations. Between operations,
the drivers are set to high-Z.
Table 4: Output Signal Level as a Function of the V
REF
V
REF
Voltage on Target
System (VDC)
Output Signal
Levels (VDC)
Status LED
Color