Datasheet

Platform Cable USB
DS300 (v3.3) June 25, 2014 www.xilinx.com
Product Specification 13
R
Refer to Figure 23 to determine the expected value of
V
REF_A
as a function of V
REF
.
Input Receiver Structure
A Schottky diode is used to protect the TDO_DONE_MISO
voltage comparator (Figure 24). In effect, Platform Cable
USB looks for voltages below V
IL
MAX to detect logic 0, and
tolerates voltages much higher than V
REF_A
because TDO
could be terminated to a supply other than V
REF
.
Signal Integrity
Platform Cable USB uses high-slew-rate buffers to drive
TCK_CCLK_SCK, TMS_PROG_SS, and TDI_DIN_MOSI.
Each buffer has a 30Ω series termination resistor. Users
should pay close attention to PCB layout to avoid
transmission line effects. Visit the Xilinx Signal Integrity
Central website, and see specifically Xilinx Application Note
XAPP361, Planning for High Speed XC9500XV Designs, for
detailed signal integrity assistance.
If the target system has only one programmable device, the
2 mm connector should be located as close as possible to
the target device. If there are multiple devices in a single
chain on the target system, users should consider buffering
TCK_CCLK_SCK. Differential driver/receiver pairs provide
excellent signal quality when the rules identified in
Figure 25 are followed. Buffering is essential if target
devices are distributed over a large PCB area.
Each differential driver and/or receiver pair contributes
approximately 5 ns of propagation delay. This is
insignificant when using 12 MHz or slower clock speeds.
Each differential receiver can drive multiple target devices if
there are no branches on the PCB trace and the total trace
length is less than four inches. A series termination resistor
should be placed adjacent to the single-ended output of the
differential receiver.
Note:
If the target system incorporates a buffer for
TCK_CCLK_SCK and the 24 MHz clock rate is used, it is
recommended that the same buffer type also be provided for
TMS_PROG_SS. This maintains a consistent phase relationship
between TCK_CCLK_SCK and TMS_PROG_SS. A buffer is not
needed for TDI_DIN_MOSI, because it sees only one load.
X-Ref Target - Figure 22
Figure 22: Target Interface Driver Topology
X-Ref Target - Figure 23
Figure 23: V
REF_A
as a Function of V
REF
X-Ref Target - Figure 24
Figure 24: Target Interface Receiver Topology
I/O
XFCE PIN
V
CC33_SW
CPLD
2 mm Connector
Internal
Three-State
Control
High-Z
V
REF_A
V
REF_A
NC7SZ125
DS300_22_120904
DS300_22_113004
I/O
XFCE PIN
CPLD
2 mm Connector
V
REF_A
V
CC33
BAT54
LT1719
DS300_23_120904
X-Ref Target - Figure 25
Figure 25: Differential Clock Buffer Example
SN65LVDS105
Four Differential
Drivers
SN65LVDS2 (2)
TCK_CCLK
TCK_CCLK_1
1
4
TCK_CCLK_4
DS300_24_110804
Locate driver package adjacent to 2mm connector
Route A & B traces for each differential
pair in parallel with equal length and
consistent spacing
Series Termination Resistor
Locate one receiver adacent
to each target device
Four
Buffered
Clocks