Datasheet

Platform Cable USB
DS300 (v3.3) June 25, 2014 www.xilinx.com
Product Specification 14
R
Target System Connections
Multiple devices can be cascaded when using either JTAG
or slave-serial topology in target systems. Figure 27,
page 14 shows typical JTAG connections, and Figure 28,
page 15 shows an example of slave-serial routing.
The Platform Cable USB can connect directly to a single
SPI flash device. Figure 26 shows example SPI flash
connections. Refer to XAPP951
, Configuring Xilinx FPGAs
with SPI Serial Flash, for a detailed reference design
showing the cable connections for programming an FPGA
bitstream into a SPI flash device.
The DONE pin on FPGAs can be programmed to be an
open-drain or active driver. For cascaded slave-serial
topologies, an external pull-up resistor should be used, and
all devices should be programmed for open-drain operation.
If the 2 mm connector is located a significant distance from
the target device, it is best to buffer TCK_CCLK_SCK, at a
minimum. These diagrams are intended to represent the
logical relationship between Platform Cable USB and target
devices. Refer to "Signal Integrity," page 13 for additional
buffering and termination information.
X-Ref Target - Figure 26
Figure 26: Example of SPI Topology
+3.3V
2 mm
Connector
VCC
GND
+3.3V
SPI Bus
(3)
V
REF
2
GND
(2)
X
ST Micro
M25Pxx
(1)
Serial Flash
MISO
D
8
MOSI
Q
10
SS
S
4
SCK C6
W
HOLD
‘1’
‘1’
Notes:
1. The example shows pin names for an STMicrosystems M25Pxx serial flash
device. SPI flash devices from other vendors can have different pin names
and requirements. See the SPI flash data sheet for the equivalent pins and
device requirements.
2. Attach the following 2 mm connector pins to digital ground: 1, 3, 5, 7, 9, 11, 13.
3. Typically, an FPGA and other sl
ave SPI devices, which are not shown, are
connected to the SPI bus. The other devices on the SPI bus must be disabled
when the cable is connected to the 2 mm connector to avoid signal contention.
When a Xilinx FPGA is connected to the SPI bus, the FPGA PROG_B pin can
be held Low to ensure the FPGA pins are kept in a high-impedance state.
DS300_30_011414
X-Ref Target - Figure 27
Figure 27: Example of JTAG Chain Topology
ISP
PROM
TDOTDI
TCKTMS
FPGA
DS300_26_031006
TDI
TCKTMS
CPLD
TDOTDI
TCKTMS
TMS
TCK
TDI
TDO
GND
(2)
V
REF
2
X
8
10
4
6
2 mm
Connector
TDO
V
CCAUX
(1)
Notes:
1. Example implies that V
CCO
, V
CCJ
, V
CC_CONFIG
and V
CCAUX
for various devices are set to the
same voltage. See device data sheets for appropriate JTAG voltage-supply levels.
2. Attach the following 2 mm connector pins to digital ground: 1, 3, 5, 7, 9, 11, 13.