Datasheet

Platform Cable USB
DS300 (v3.3) June 25, 2014 www.xilinx.com
Product Specification 17
R
Interface Pin Descriptions
Tabl e 5: SS/JTAG/SPI Port: 14-Pin Ribbon Cable Connector
Ribbon
Cable
Number
Slave-Serial
Configuration
Mode
JTAG
Configuration
Mode
SPI
(2)
Programming
Mode
Type Description
2V
REF
V
REF
–In
Target Reference Voltage.
(3)
This pin should be connected to a
voltage bus on the target system that serves the JTAG, slave-serial
interface. or SPI. For example, when programming a Coolrunner-II
device using the JTAG port, V
REF
should be connected to the
target V
AUX
bus.
4PROG – –Out
Configuration Reset. This pin is used to force a reconfiguration of
the target FPGA(s). It should be connected to the PROG_B pin of
the target FPGA for a single-device system, or to the PROG_B pin
of all FPGAs in parallel in a daisy-chain configuration.
6 CCLK – – Out
Configuration Clock. FPGAs load one configuration bit per CCLK
cycle in slave-serial mode. CCLK should be connected to the
CCLK pin on the target FPGA for a single-device configuration, or
to the CCLK pin of all FPGAs in parallel in a daisy-chain
configuration.
8DONE – – In
Configuration Done. This pin indicates to Platform Cable USB
that target FPGAs have received the entire configuration bitstream.
It should be connected to the Done pin on all FPGAs in parallel for
daisy-chained configurations. Additional CCLK cycles are issued
following the positive transition of Done to insure that the
configuration process is complete.
10 DIN – – Out
Configuration Data Input. This is the serial input data stream for
target FPGAs. It should be connected to the DIN pin of the target
FPGA in a single-device system, or to the DIN pin of the first FPGA
in a daisy-chain configuration.
12 N/C N/C – –
Reserved. This pin is reserved for Xilinx diagnostics and should
not be connected to any target circuitry.
14 INIT – – BIDIR
Configuration Initialize. This pin indicates that configuration
memory is being cleared. It should be connected to the INIT_B pin
of the target FPGA for a single-device system, or to the INIT_B pin
on all FPGAs in parallel in a daisy-chain configuration.
4– TMS –Out
Test Mode Select. This is the JTAG mode signal that establishes
appropriate TAP state transitions for target ISP devices. It should
be connected to the TMS pin on all target ISP devices that share
the same data stream.
6– TCK –Out
Test Clock. This is the clock signal for JTAG operations, and
should be connected to the TCK pin on all target ISP devices that
share the same data stream.
8– TDO –In
Test Data Out. This is the serial data stream received from the
TDO pin on the last device in a JTAG chain.
10 – TDI – Out
Test Data In. This is the serial data stream transmitted to the TDI
pin on the first device in a JTAG chain.
10 – – MOSI Out
SPI Master-Output Slave-Input. This pin is the target serial input
data stream for SPI operations and should be connected to the D
(2)
pin on the SPI flash PROM.
8– – MISOIn
SPI Master-Input, Slave-Output. This pin is the target serial
output data stream for SPI operations and should be connected to
the Q
(2)
pin on the SPI flash PROM.
6– – SCKOut
SPI Clock. This pin is the clock signal for SPI operations and
should be connected to the C
(2)
pin on the SPI flash PROM.
4– – SSOut
SPI Select. This pin is the active-Low SPI chip select signal. This
should be connected to the S
(2)
pin on the SPI flash PROM.