Datasheet

Platform Cable USB
DS300 (v3.3) June 25, 2014 www.xilinx.com
Product Specification 19
R
Tabl e 8: AC Operating Characteristics
Symbol Description Conditions Min Max Units
T
CLK
Clock Period
TCK_CCLK_SCK_S
CK frequency:
750 kHz 41.66 ns
24 MHz 1333 ns
T
CPD
Cable Propagation Delay Time
TDI_DIN_MOSI (TMS_PROG_SS)
relative to the negative edge
of TCK_CCLK_SCK @ 24 MHz
Target system V
REF
:
3.3V 9.2 ns
2.5V TBD ns
1.8V TBD ns
T
TSU
Target Setup Time
TDI_DIN_MOSI (TMS_PROG_SS)
relative to the positive edge
of TCK_CCLK_SCK @ 24 MHz
Target system V
REF
:
3.3V 11 ns
2.5V TBD ns
1.8V TBD ns
T
CSU
Cable Setup Time
TDO_DONE_MISO relative to the
positive edge
of TCK_CCLK_SCK @ 24 MHz
Target system V
REF
:
3.3V 11 ns
2.5V TBD ns
1.8V TBD ns
T
TPD
Target Propagation Delay Time
TDO_DONE_MISO relative to the
negative edge
of TCK_CCLK_SCK @ 24 MHz
Target system V
REF
:
3.3V 10 ns
2.5V TBD ns
1.8V TBD ns
X-Ref Target - Figure 30
Figure 30: Platform Cable USB Timing Diagram
TCK_CCLK_SCK
T
TSU
T
CLK
TDO_DONE_MISO
T
CSU
T
CPD
T
TPD
DS300_28_021707
Notes:
1. All times are in nanoseconds and are relative to the target system interface connector.
2. T
TSU
Min is the minimum setup time guaranteed by Platform Cable USB relative to the positive edge of TCK_CCLK_SCK.
3. T
CSU
Min is the minimum setup required by Platform Cable USB to properly sample TDO_DONE_MISO.
4. Propagation delays associated with buffers on the target system must be taken into account to satisfy the minimum setup times.
Target device samples TMS_PROG_SS and
TDI_DIN_MOSI on positive edge of TCK_CCLK_SCK
Target device asserts TDO_DONE_MISO
on negative edge of TCK_CCLK_S
CK
Platform cable USB samples
TDO_DONE_MISO approxi-
mately 15 ns after positive
edge of TCK_CCLK_SCK
TMS_PROG_SS/
TDI_DIN_MOSI
Platform Cable USB asserts
TMS_PROG_SS and TDI_DIN_MOSI
on negative edge of TCK_CCLK_SCK