Data Sheet

PYNQ-Z1 Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
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Page 15 of 25
Figure 11.1 outlines the clocking scheme used on the PYNQ-Z1. Note that the reference clock output from the
Ethernet PHY is used as the 125 MHz reference clock to the PL, in order to cut the cost of including a dedicated
oscillator for this purpose. Keep in mind that CLK125 will be disabled when the Ethernet PHY (IC1) is held in
hardware reset by driving the PHYRSTB signal low.
Figure 11.1. PYNQ-Z1 clocking.
12 Basic I/O
The PYNQ-Z1 board includes two tri-color LEDs, 2 switches, 4 push buttons, and 4 individual LEDs as shown in
Figure 12.1. The push buttons and slide switches are connected to the Zynq PL via series resistors to prevent
damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button or slide
switch was inadvertently defined as an output). The four push buttons are “momentary” switches that normally
generate a low output when they are at rest, and a high output only when they are pressed. Slide switches
generate constant high or low inputs depending on their position.
Figure 12.1. PYNQ-Z1 GPIO.
The four individual high-efficiency LEDs are anode-connected to the Zynq PL via 330-ohm resistors, so they will
turn on when a logic high voltage is applied to their respective I/O pin. Additional LEDs that are not user-accessible
indicate power-on, PL programming status, and USB and Ethernet port status.